US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 182

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US38024-BAG1

Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet

Specifications of US38024-BAG1

Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 6 ROM
6.5.4
Table 6.5 lists the register configuration to control the flash memory when the built in flash
memory is effective.
Table 6.5
Register Name
Flash memory control register 1
Flash memory control register 2
Flash memory power control register
Erase block register
Flash memory enable register
Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is
6.6
6.6.1
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash
Memory Programming/Erasing. By setting this register, the flash memory enters program mode,
erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0
of this register are cleared when using flash memory as normal built-in ROM.
Bit 7—Reserved
This bit is always read as 0 and cannot be modified.
Rev. 8.00 Mar. 09, 2010 Page 160 of 658
REJ09B0042-0800
Bit
Initial value
Read/Write
enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which PROM or ROM is included does not have
these registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.
Register Configuration
Descriptions of Registers of the Flash Memory
Flash Memory Control Register 1 (FLMCR1)
Register Configuration
7
0
SWE
R/W
6
0
ESU
R/W
5
0
Abbreviation
FLMCR1
FLMCR2
FLPWCR
EBR
FENR
PSU
R/W
4
0
R/W
R/W
R
R/W
R/W
R/W
R/W
EV
3
0
Initial Value
H'00
H'00
H'00
H'00
H'00
R/W
PV
2
0
R/W
E
1
0
Address
H'F020
H'F021
H'F022
H'F023
H'F02B
R/W
P
0
0

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