US38024-BAG1 Renesas Electronics America, US38024-BAG1 Datasheet - Page 97
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US38024-BAG1
Manufacturer Part Number
US38024-BAG1
Description
DEV EVALUATION KIT H8/38024
Manufacturer
Renesas Electronics America
Series
H8®r
Type
MCUr
Datasheet
1.US38024-BAG1.pdf
(684 pages)
Specifications of US38024-BAG1
Contents
2G (Second-generation) Evaluation Board, HEW debugger support, Cable and CD-ROM
For Use With/related Products
H8/38024
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 97 of 684
- Download datasheet (5Mb)
3.1
Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT
Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of
these two types of exception handling.
Table 3.1
Priority
High
Low
3.2
3.2.1
A reset is the highest-priority exception. The internal state of the CPU and the registers of the on-
chip peripheral modules are initialized.
3.2.2
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
I bit of the condition code register (CCR) set to 1.
which the program starts executing from the address indicated in PC.
Overview
Reset
Overview
Reset Sequence
Exception Source
Reset
Interrupt
Exception Handling Types and Priorities
Section 3 Exception Handling
Time of Start of Exception Handling
Exception handling starts as soon as the reset state is cleared
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Rev. 8.00 Mar. 09, 2010 Page 75 of 658
Section 3 Exception Handling
REJ09B0042-0800
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