MC908GZ60CFJE Freescale Semiconductor, MC908GZ60CFJE Datasheet - Page 149

• Manufacturer Part Number: MC908GZ60CFJE
• Description: IC MCU 60K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GZ60CFJE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 2KB
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: CAN, SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC08GZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, ESCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 8
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See
12.13.3 MSCAN08 Bus Timing Register 0
Table 12-8
Freescale Semiconductor
gives an overview on the CAN conforming segment settings and the related parameter values.
Segment 1
It is the user’s responsibility to make sure that the bit timing settings are in
compliance with the CAN standard,
5 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
9 .. 16
Time
Table 12-4. CAN Standard Compliant Bit Time Segment Settings
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
SYNC
_SEG
Transmit point
Sample point
SYNC_SEG
1
Figure 12-9. Segments Within the Bit Time
TSEG1
3 .. 10
4 .. 11
5 .. 12
6 .. 13
7 .. 14
8 .. 15
4 .. 9
Table 12-3. Time Segment Syntax
System expects transitions to occur on the bus during this
period.
A node in transmit mode will transfer a new value to the CAN
bus at this point.
A node in receive mode will sample the bus at this point. If the
three samples per bit option is selected then this point marks
the position of the third sample.
NRZ SIGNAL
(PROP_SEG + PHASE_SEG1)
8... 25 TIME QUANTA
TIME SEGMENT 1
= 1 BIT TIME
Segment 2
and
4 ... 16
Time
2
3
4
5
6
7
8
12.13.4 MSCAN08 Bus Timing Register
NOTE
.
TSEG2
1
2
3
4
5
6
7
SAMPLE POINT
(SINGLE OR TRIPLE SAMPLING)
(PHASE_SEG2)
Synchronized
TIME SEG. 2
Jump Width
2 ... 8
1 .. 2
1 .. 3
1 .. 4
1 .. 4
1 .. 4
1 .. 4
1 .. 4
0 .. 1
0 .. 2
0 .. 3
0 .. 3
0 .. 3
0 .. 3
0 .. 3
SJW
1.
Clock System
149