EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 131

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
5.1.5.2 Bus and Peripheral Clock Generation
Both PLLs are software programmable (each value is defined in
“ClkSet2” on page 5-20
determined by:
Here PLL1_X1FBD, PLL1_X2FBD, PLL1_X2IPD and PLL1_PS are the bit fields in the
"ClkSet1"
The same conditions apply to PLL2 and the
Figure 5-2
• PLL1_X1 desired reference clock frequency range is > 11.058 MHz and < 200 MHz
• PLL1_X1 output frequency range is > 294 MHz and < 368 MHz
• PLL1_X2 desired reference clock frequency (after PLL1_X2IPD divider) is > 12.9 MHz
• PLL1_X2 output, BEFORE the PS divide, must be > 290 MHz and <= 528 MHz
and < 200 MHz.
register. The user must be aware of the requirements of PLL operation. They are:
illustrates the clock generation system.
Fout
registers, respectively). The frequency of output clock Fout is
=
14.7456MHz
Copyright 2007 Cirrus Logic
⋅
(
--------------------------------------------------------------------------------------------------------- -
"ClkSet2"
PLL1_X1FBD
(
PLL1_X2IPD
register.
+
1
)
“ClkSet1” on page 5-18
×
+
(
1
PLL1_X2FBD
)
×
2
PLL1_PS
EP93xx User’s Guide
System Controller
+
1
)
and
5-5
5