EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 795

IC ARM9 SOC PROCESSOR 208LQFP

EP9301-CQZ

Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9301-CQZ

Core Size
16/32-Bit
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
 Details
Other names
598-1136

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DS785UM1
28.1.3 Reset
All GPIO registers are initialized on system reset. The data and data direction registers for all
ports (except as noted below) are cleared, configuring them as inputs. Port E[1:0] bits are
used for the LED outputs RDLED and GRLED respectively and are set to drive high. Port
G[3:2] bits are used for SLA[1:0] outputs and are set to drive low. Port G[1:0] bits are used
for EEDAT and EECLK respectively and are set up as inputs. All interrupt control and
debounce registers are cleared.
to PRDATA[7:0]
Figure 28-3. Signal Connections Within the Enhanced GPIO Port Control Logic
Enhanced GPIO Ports A, B, and F
DDR
DR
TISR
DB
INTEN
INTTYPE1
INTTYPE2
Register
Read
Select
DATA
EDGE
Copyright 2007 Cirrus Logic
ENA
POL
OE
OE
OE
(Ports A, B, F)
TESTRDSEL
1
0
INTERRUPT
CONTROL
LOGIC
TESTINPSEL
OE[7:0]
DATA[7:0]
0
1
CLK
IN
EP93xx User’s Guide
EP[7:0]
GPIO Interface
ICLK
28-5
28

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