EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 236

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

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7-54
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
BLKPOL:
HSPOL:
V/CPOL:
CSYNC:
DATEN:
SYNCEN:
Copyright 2007 Cirrus Logic
1 - Pixel data output changes on falling edge of the clock
on the SPCLK pin
Blank Polarity - Read/Write
The value written to this bit selects the polarity of the
blanking signal on the BLANK pin:
0 - BLANK is active LOW (default)
1 - BLANK is active HIGH
Horizontal Sync Polarity - Read/Write
The value written to this bit selects the polarity of the
horizontal synchronization signal on the HSYNC pin:
0 - HSYNC is active LOW (default)
1 - HSYNC is active HIGH
Vertical / Composite Polarity - Read/Write
The value written to this bit selects the polarity of the
synchronization signal on the V_CSYNC pin:
0 - V_CSYNC is active LOW (default)
1 - V_CSYNC is active HIGH
Composite Sync - Read/Write
The value written to this bit selects whether the Vertical
Sync or the Composite Sync signal is routed to the
V_CSYNC pin:
0 - Vertical Sync
1 - Composite Sync
Pixel Data Enable - Read/Write
The value written to this bit selects whether pixel data is
output to the P[x] pins, or not:
0 - Pixel data output disabled
1 - Pixel data output enabled
Video Sync Enable - Read/Write
The value written to this bit selects whether
synchronization signals are output to the H_SYNC and
V_CSYNC pins, or not:
0 - Video SYNC outputs disabled
1 - Video SYNC outputs enabled
DS785UM1