EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 223

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

VClkStrtStop
DS785UM1
31
15
Address: 0x8003_000C
Default: 0x0000_0000
Definition: Vertical Clock Start/Stop register
Bit Descriptions:
30
14
RSVD
RSVD
29
13
28
12
RSVD:
STOP:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Stop - Read/Write
The STOP timing register contains the value of the Vertical
down counter at which the VCLKEN signal goes inactive
(stops). This indicates the end of the video clock for the
Vertical frame. Please refer to video signalling timing
diagrams in
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
STRT:Start - Read/Write
The STRT timing register contains the value of the Vertical
down counter at which the VCLKEN signal becomes
active (starts). This indicates the start of the video clock for
the Vertical frame. Please refer to video signalling timing
diagrams in
internal block signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
Figure 7-9
Figure 7-9
22
6
STOP
STRT
and
and
21
5
Figure
Figure
20
4
7-10. VCLKEN is an
7-10. VCLKEN is an
19
3
EP93xx User’s Guide
18
2
17
1
16
7-41
0
7