EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 148

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

5
ScratchReg0, ScratchReg1
APBWait
5-22
System Controller
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
Definition:
Bit Descriptions:
30
14
30
14
29
13
29
13
28
12
28
12
ScratchReg0 - 0x8093_0040, Read/Write
ScratchReg1 - 0x8093_0044, Read/Write
0x0000_0000
Each of these locations provide a 32-bit read/write scratch register, that can be
used as a general purpose storage. These registers are reset to zero only on a
power-on-reset. A System Reset will have no effect.
Value:
0x8093_0050, Read/Write
The APBWait register controls the insertion of wait states for APB peripherals.
RSVD:
NO_WRITE_WAIT:Used in the AHB/APB bridge to not insert an AHB wait
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
9
25
9
This is a 32-bit read/write location.
Reserved. Unknown During Read.
during writes, if set. If reset, a wait state is added by
forcing HREADY = 0 during ST_WRITE. This bit resets to
0x0001.
RSVD
24
8
24
8
RSVD
Value
Value
23
7
23
7
22
6
22
6
21
5
21
5
20
4
20
4
19
3
19
3
18
2
18
2
17
1
NO_WRITE_WAIT
17
1
DS785UM1
16
0
16
0