EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 559

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
15.2.1 IrDA SIR Encoder/decoder Functional Description
15.1 Introduction
15.2 IrDA SIR Block
UART2 implements a UART interface identical to that of UART1. UART2 does not implement
a modem or HDLC interface. For additional details about UART1, refer to
“UART1 With HDLC and Modem Control Signals” on page
UART2 and the IrDA blocks cooperatively implement a Slow Infrared (SIR) interface. The
register interface for each block is separate. The UART2 control registers are at base
address 0x808D_0000 and the IrDA controller registers are at base address 0x808B_0000.
For additional details about IrDA, refer to
interface is described below.
The IrDA SIR block contains an IrDA SIR protocol Encoder/decoder. The SIR protocol
Encoder/decoder can be enabled for serial communication via signals nSIROUT and SIRIN
to an infrared transducer instead of using the UART signals UARTTXD and UARTRXD.
If the SIR protocol Encoder/decoder is enabled, the UARTTXD line is held in the passive
state (HIGH) and transitions of the modem status or the UARTRXD line will have no effect.
The SIR protocol Encoder/decoder can both receive and transmit, but it is half-duplex only, so
it cannot receive while transmitting, or vice versa.
The IrDA SIR physical layer specifies a minimum 10 ms delay between transmission and
reception.
The IrDA SIR Encoder/decoder comprises:
This is shown in
• IrDA SIR transmit encoder
• IrDA SIR receive decoder
Figure
15-1:
Copyright 2007 Cirrus Logic
Chapter
17,
“IrDA” on page
14-1.
17-1. The UART SIR
Chapter 15
Chapter
15UART2
14,
15-1
15