EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 570
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUS
Quantity:
3 390
Part Number:
EP9301-CQZ
Manufacturer:
CIRRUSLOGIC
Quantity:
20 000
Company:
Part Number:
EP9301-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
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15
UART2Ctrl
15-12
UART2
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808D_0014 - Read/Write
0x0000_0000
UART Control Register
RSVD:
LBE:
RTIE:
TIE:
RIE:
MSIE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Loopback Enable, for SIR and UART only.
1 - If the SIR Enable bit is also set to “1”, and register
UART2TMR bit 1 (SIRTEST) is set to “1”, the SIR output
path is inverted and fed through to the SIR input path. The
SIRTEST bit in the test register must be set to “1” to
override the normal half-duplex SIR operation. This should
be the requirement for accessing the test registers during
normal operation, and SIRTEST must be cleared to “0”
when loopback testing is finished. This feature reduces the
amount of external coupling required during system test.
0 - This bit is cleared to “0” on reset, which disables the
loopback mode.
Receive Timeout Enable. If this bit is set to “1”, the receive
timeout interrupt is enabled.
Transmit Interrupt Enable. If this bit is set to “1”, the
transmit interrupt is enabled.
Receive Interrupt Enable. If this bit is set to “1”, the receive
interrupt is enabled.
Modem Status Interrupt Enable. If this bit is set to “1”, the
modem status interrupt is enabled.
24
8
RSVD
LBE
23
7
RTIE
22
6
TIE
21
5
RIE
20
4
MSIE
19
3
SIRLP
18
2
SIREN
17
1
DS785UM1
UARTE
16
0
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