EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 430
EP9301-CQZ
Manufacturer Part Number
EP9301-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-CQZ
Core Size
16/32-Bit
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-TQFP, 208-VQFP
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
166MHz
No. Of Timers
4
Digital Ic Case Style
TQFP
Embedded Interface Type
SPI
Rohs Compliant
Yes
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1136
Available stocks
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Manufacturer
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Price
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Part Number:
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Manufacturer:
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Part Number:
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Manufacturer:
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10
10-36
DMA Controller
EP93xx User’s Guide
Definition:
Bit Descriptions:
This is the interrupt status register. The register is read to obtain interrupt
status for enabled interrupts. An interrupt is enabled by writing the
corresponding bits in the CONTROL register.
Write this location once to clear the interrupt. (See the Interrupt Register Bit
Descriptions for the bits where this applies.)
RSVD:
STALLInt:
DONEInt:
NFBInt:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Indicates channel has stalled. This interrupt is generated
on a Channel State machine transition from MEM_RD
(memory read) or MEM_WR (memory write) to the STALL
state, assuming STALLIntEn set. The interrupt is cleared
by either disabling the channel or by triggering a new
transfer.
Transaction is done. When enabled, this interrupt is set
when all DMA controller transactions complete normally,
as determined by the transfer count/external peripheral
DEOT signal. When a transfer completes, software must
clear the DONE bit before reprogramming the DMA, by
writing either a “0” or “1” to this bit. This must be done
even if the DMA interrupt is disabled. The DMA will ignore
any additional DREQs that it receives from the external
peripheral (if operating in external DMA mode) until the
software clears the DONE interrupt and reprograms the
DMA with new BCRx values.
Indicates that a channels buffer descriptor is free for
update. This interrupt is generated if NFBIntEn is set,
when a transfer begins using the second buffer of the
double-buffer set, thus informing software that it can now
set up the other buffer. The interrupt is cleared by either
disabling the channel or writing a new BCR value to set up
a new buffer descriptor. The interrupt is not generated for
a single-buffer transfer. In software triggered M2M mode,
servicing of the NFB interrupt is dependent on the system
level AHB arbitration since the DMA’s HREQ (AHB
request) may be continuously held high.
DS785UM1
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