EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 631

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

FISR
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808B_0180 - Read/Write
0x0000_0000
FIR Status Register.
RSVD:
RFL:
RIL:
RFC:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Receive Frame Lost. Set to a “1” when a ROR occurred at
the start of a new frame, before any data for the frame
could be put into the receive FIFO. This bit is cleared by
writing a “1” to this bit. This occurs if the last entry in the
FIFO already contains a valid EOF bit from a previous
frame when a FIFO overrun occurs. The ROR bit cannot
be placed into the FIFO and all data associated with the
frame is lost.
Receive Information Buffer Lost. Set to a “1” when the last
data for a frame is read from the receive FIFO (via the
IrData register) and the RFC bit is still set from a previous
end of frame. It indicates that data in the IrRIB register for
the previous frame was lost. This can occur if the CPU
does not respond to the RFC interrupt before another
frame completes and is read from the IrData register by
the DMA controller. This bit is cleared by writing a “1” to
this bit.
Received Frame Complete. Set to “1” when the last data
for a frame is read from the receive FIFO (via the IrData
register). This event also triggers the IrRIB to load the
IrFlag and byte count. This bit is cleared when the IrRIB
register is read.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
EP93xx User’s Guide
TAB
18
2
TFC
17
1
17-35
TFS
IrDA
16
0
17