EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 621

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

IrAdrMatchVal
DS785UM1
31
15
Address:
Default:
Definition:
30
14
29
13
28
12
TXP:
RXE:
TXE:
TUS:
BRD:
0:
0x808B_0008 - Read/Write
0x0000_0000
IrDA Address Match Value Register contains the 8 bit address match value
field which is used by the receiver to selectively store only the data within the
receive frames which have the same address. For incoming frames which
have the same address value as the AMV field, the frame’s address, control
and data is stored in the receive buffer. For those that do not match, the
remainder of the frame is ignored and the receive logic searches for the
beginning of the next frame. This register is used for both MIR and FIR. The
AME bit in IrCtrl must be set to enable this function. Frames containing an
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Transmit Polarity Control.
0 - Encoded data is not inverted before being passed to
the pins.
1 - Encoded data is inverted before being passed to the
pins.
Receive Enable.
0 - Ir receive logic is disabled and clocks are stopped.
1 - Ir receive logic is enabled.
Transmit Enable.
0 - Transmit logic is disabled and clocks are stopped.
1 - Transmit logic is enabled.
Transmit buffer Underrun Select.
0 - Transmit buffer underrun causes CRC, stop flag, and
SIP to be transmitted.
1 - Transmit buffer underrun causes an abort to be
transmitted.
MIR Bit rate select.
0 - MIR data rate is 0.576 Mbit/s.
1 - MIR data rate is 1.152 Mbit/s.
Must be written to “0”.
24
8
RSVD
23
7
22
6
21
5
20
4
AMV
19
3
EP93xx User’s Guide
18
2
17
1
17-25
IrDA
16
0
17