EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 455

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

HcCommandStatus
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RWE:
0x8002_0008
0x0000_0000
Provides current controller status and accepts controller commands.
RSVD:
HCR:
27
11
26
10
RSVD
Copyright 2007 Cirrus Logic
25
9
RemoteWakeupEnable:
This bit is used by HCD to enable or disable the remote
wakeup feature upon the detection of upstream resume
signaling. When this bit is set and the ResumeDetected bit
in HcInterruptStatus is set, a remote wakeup is signaled to
the host system. Setting this bit has no impact on the
generation of hardware interrupt.
Reserved. Unknown During Read.
HostControllerReset:
This bit is set by HCD to initiate a software reset of HC.
Regardless of the functional state of HC, it moves to the
USBSUSPEND state in which most of the operational
registers are reset except those stated otherwise; e.g., the
InterruptRouting field of HcControl, and no Host bus
accesses are allowed. This bit is cleared by HC upon the
completion of the reset operation. The reset operation
must be completed within 10 ms. This bit, when set,
should not cause a reset to the Root Hub and no
subsequent reset signaling should be asserted to its
downstream ports.
RSVD
24
8
23
7
22
6
21
5
Universal Serial Bus Host Controller
20
4
OCR
19
3
EP93xx User’s Guide
BLF
18
2
CLF
17
1
SOC
11-15
HCR
16
0
11