EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 305

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
9.1.2 MAC Engine
9.1.2.1 Data Encapsulation
The RAM blocks are interleaved in the AHB address space. AHB address bits 0 and 1 are
byte selects and must be zero for direct access. AHB address bit 2 selects the left or right
RAM array, which is the Transmit or Receive array. AHB address bits 3,4, and 5 perform a 1-
of-8 column select. Address bit 6 selects the even or odd row address. Address bits 7, 8, 9,
and 10 decode the rows. Thus from an AHB addressing perspective, the MAC FIFOs are one
large RAM array.
Table 9-1
are in byte units. All data transfers to the FIFO RAM are restricted to words.
Caution: Accessing the FIFO RAM while the MAC is operating will likely cause a
malfunction.
There is no arbitration logic between direct AHB access and MAC Descriptor Processor
access.
The MAC configurations registers and FIFO RAMs are only word accessible
The MAC engine is compliant with the requirements of ISO/IEC 8802-3 (1993), Sections 3
and 4.
In transmission, the MAC automatically prepends the preamble, and computes and appends
the FCS. The data after the SFD and before the FCS is supplied by the host as the
transmitted data. FCS generation by the MAC may be disabled by setting InhibitCRC bit in
the Transmit Frame Descriptor. Refer to
defines the FIFO RAM address map as it appears in the address space. Address
0x8001_4800 to 0x8001_4FFF
0x8001_5080 to 0x8001_50BF
0x8001_50C0 to 0x8001_50FF
0x8001_4000 to 0x8001_47FF
0x8001_5000 to 0x8001_503F
0x8001_5040 to 0x8001_507F
FIFO RAM Address Map
Copyright 2007 Cirrus Logic
Table 9-1. FIFO RAM Address Map
Figure
9-2.
1/10/100 Mbps Ethernet LAN Controller
Rx Descriptor
Tx Descriptor
Rx Status
Tx Status
Rx Data
Tx Data
Usage
EP93xx User’s Guide
9-3
9