EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 710

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

22
AC97Reset
22-22
AC’97 Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x8088_00A0 - Read/Write
Controller Reset Register. The AC’97 Controller RESET register is a
read/write register that controls various functions within the AC’97 Controller
of the RESET port. All the register bits are cleared to “0” when reset.
RSVD:
EFORCER:
FORCEDRESET: If the EFORCER bit is set to “1”, the RESET port will follow
TIMEDRESET:
27
11
26
10
Copyright 2007 Cirrus Logic
RSVD
25
9
Reserved. Unknown During Read.
Enable for the Forced RESET bit.
1 - FORCEDRESET become active
0 - FORCEDRESET has no effect.
whatever value is written to this bit. If this mechanism is
used to control the RESET port, it is up to software to
ensure that the signal is high long enough to meet the
specification of the external device.
This bit has priority over the TIMEDRESET bit.
If this bit is set to “1”, the RESET port is forced to “0” for
five pulses of the 2.9491 MHz clock
(0.339 µs x 5 = 1.695 µs maximum reset pulse and
1.356 µs minimum reset pulse using this 2.9491 MHz
clock). After which this bit is zeroed.
24
8
23
7
22
6
21
5
20
4
19
3
EFORCER
18
2
FORCED
RESET
17
1
DS785UM1
RESET
TIMED
16
0