EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 450

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

11
11-10
Universal Serial Bus Host Controller
EP93xx User’s Guide
11.2.5.4 HCI Master Block
11.2.5.5 USB State Control
11.2.5.6 Data FIFO
11.2.5.7 List Processor
11.2.5.8 Root Hub and Host SIE
The HCI Master Block handles read/write requests to system memory that are initiated by the
List Processor while the Host Controller (HC) is in the operational state and is processing the
lists queued in by HCD. It generates the addresses for all the memory accesses, which is the
DMA functionality. The major tasks handled by this block are:
This block implements:
This block contains a 64x8 FIFO to store the data returned by endpoints on IN tokens, and
the data to be sent to the endpoints on OUT Tokens. The FIFO is used as a buffer in case the
HC does not get timely access to the host bus.
The List Processor processes the lists scheduled by HCD according to the priority set in the
operational registers.
The Root Hub propagates Reset and Resume to downstream ports and handles port connect
and disconnect. The Host Serial Interface Engine (HSIE) converts parallel to serial, serial to
parallel, Non-Return to Zero Interface (NRZI) encoding/decoding and manages USB serial
protocol.
• Fetching Endpoint Descriptors (ED) and Transfer Descriptors (TD)
• Read/Write endpoint data from/to system memory
• Accessing HC Communication Area (HCCA)
• Write Status and Retire TDs
• The USB operational states of the Host Controller, as defined in the OHCI Specification.
• It generates SOF tokens every 1 ms
• It triggers the List Processor while HC is in the operational states.
Copyright 2007 Cirrus Logic
DS785UM1