EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 667

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
The first three can have their interrupt level determined by I2STXCtrl[0]. If this bit = 1, then
the FIFO empty interrupt will occur when the FIFO is empty. If this bit = 0, then the FIFO
empty interrupt will occur when the FIFO is half empty.
All four are combined and are maskable with the TX interrupt register enable bit,
I2STXCtrl[1].
The FIFO empty internal interrupts are cleared if the FIFO’s are filled with data or the
corresponding channel is disabled.
The TX underflow internal interrupt is cleared by writing to both the left and right data
registers of all enabled TX channels. This interrupt will also be cleared if the corresponding
channel is disabled.
The I
the status of the 3 individual RX FIFOs. These internal interrupts are as follows:
The first three can have their interrupt level determined by I2SRXCtrl[0]. If this bit = 1, then
the FIFO full interrupt will occur when the FIFO is full. If this bit = 0, then the FIFO full interrupt
will occur when the FIFO is half full.
All four are combined and are maskable with the RX interrupt register enable bit,
I2SRXCtrl[1].
The FIFO full internal interrupts are cleared if the FIFO’s become less than full or the
corresponding channel is disabled.
The RX overflow internal interrupt is cleared by reading both the left and right data registers
of all enabled RX channels. This interrupt will also be cleared if the corresponding channel is
disabled.
The RX and TX global interrupts are combined to form the I
Table 21-6
transmitter FIFO empty flag will result in an interrupt but for a receiver FIFO empty flag a
status bit only is set.
The sticky bits refer to bits I2SGlSts[11:6]. A write of zero is required to clear the setting of
these bits.
• TX2 FIFO empty.
• TX underflow.
• RX0 FIFO full.
• RX1 FIFO full.
• RX2 FIFO full.
• RX overflow.
2
S receiver generates 4 internal interrupts within the I
summarizes which FIFO flags will generate interrupts when set. For example a
Copyright 2007 Cirrus Logic
2
S controller. Each of these reflect
2
S controller Interrupt, I2SINTR.
EP93xx User’s Guide
I
2
S Controller
21-11
21