EP9301-CQZ Cirrus Logic Inc, EP9301-CQZ Datasheet - Page 501

• Manufacturer Part Number: EP9301-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-CQZ

• Core Size: 16/32-Bit
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-TQFP, 208-VQFP
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 166MHz
• No. Of Timers: 4
• Digital Ic Case Style: TQFP
• Embedded Interface Type: SPI
• Rohs Compliant: Yes
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1136

DS785UM1
Step
10
12
13
14
11
2
3
4
5
6
7
8
9
Write a ‘1’ or ‘0’ to the External Bus Width bit in the
appropriate
Write Initialize = ‘0’, MRS = ‘1’, and LCR = ‘0’ to the
"GlConfig"
Read from the external SDRAM’s Mode register
with Row and Bank address = 0x2 or 0x3 (see
SDRAM data sheet)
Write Initialize = ‘1’, MRS = ‘1’, and LCR = ‘0’ to the
"GlConfig"
Wait 200 μ s
Write Initialize = ‘1’, MRS = ‘0’, and LCR = ‘0’ to the
"GlConfig"
Write Refcnt = 0xB into the
Wait for at least 80 SDCLK cycles
Write the normal operating value to the Refcnt field
in the
Write Initialize = ‘0’, MRS = ‘1’, and LCR = ‘0’ to the
"GlConfig"
Perform a read from each SDRAM in the
"SDRAMDevCfg[3:0]"
address that is read defines the value that is
written into the Mode register (see SDRAM device
datasheet). The address value is dependent on the
configuration of the memory system since the
actual SDRAM address pins are mapped
differently onto the processor’s address pins for
16- and 32-bit wide memory systems. (This is the
reason for step 2).
Write parameters corresponding to those
programmed into the SDRAM devices Mode
register into the corresponding fields of the
"SDRAMDevCfg[3:0]"
the "SDRAMDevCfg[3:0]"register as appropriate
for the given SDRAM usage.
Write Initialize = ‘0’, MRS = ‘0’, and LCR = ‘0’ to the
"GlConfig"
"RefrshTimr"
register
register
register
register
register.
Table 13-4. General SDRAM Initialization Sequence
"SDRAMDevCfg[3:0]"
register
Action
space. The value of the
register. Write other fields in
Copyright 2007 Cirrus Logic
"RefrshTimr"
register
register
SDRAM, SyncROM, and SyncFLASH Controller
‘1’ specifies 16-bit memory bus width
‘0’ specifies 32-bit memory bus width
To allow the Mode register inside the
external SDRAM device to be accessed
0x2 -- Burst Length = 4 (32-bit wide
memory bus)
0x3 -- Burst Length = 8 (16-bit wide
memory bus)
To issue continuous NOP accesses
SDRAM requirement
To issue a Pre-Charge All accesses
To provide a refresh every 10 SDCLK
cycles
To provide 8 refresh cycles to all
SDRAMs in
space
To establish normal refresh operation
To allow the Mode register inside the
SDRAM device to be accessed
To set up the Mode register inside each
SDRAM device
To initialize the SDRAM controller timing
To start normal operation
"SDRAMDevCfg[3:0]"
Reason
EP93xx User’s Guide
13-5
13