afs600 Actel Corporation, afs600 Datasheet

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afs600

Manufacturer Part Number
afs600
Description
Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
Manufacturer
Actel Corporation
Datasheet

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Actel Fusion
Mixed-Signal Family with Optional ARM
Features and Benefits
High-Performance Reprogrammable Flash Technology
Embedded Flash Memory
Integrated A/D Converter (ADC) and Analog I/O
On-Chip Clocking Support
Table 1 •
J u ly 2 0 0 8
© 2008 Actel Corporation
Fusion Devices
ARM-Enabled
Fusion Devices
General
Information
Memory
Analog and I/Os
Notes:
1. Refer to the
2. Refer to the
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process
Nonvolatile, Retains Program when Powered Off
Live at Power-Up (LAPU) Single-Chip Solution
350 MHz System Performance
User Flash Memory – 2 Mbits to 8 Mbits
1 kbit of Additional FlashROM
Up to 12-Bit Resolution and up to 600 ksps
Internal 2.56 V or External Reference Voltage
ADC: Up to 30 Scalable Analog Input Channels
High-Voltage Input Tolerance: –10.5 V to +12 V
Current Monitor and Temperature Monitor Blocks
Up to 10 MOSFET Gate Driver Outputs
ADC Accuracy is Better than 1%
Internal 100 MHz RC Oscillator (accurate to 1%)
Crystal Oscillator Support (32 kHz to 20 MHz)
Programmable Real-Time Counter (RTC)
6 Clock Conditioning Circuits (CCCs) with 1 or 2 Integrated PLLs
Configurable 8-, 16-, or 32-Bit Datapath
10 ns Access in Read-Ahead Mode
P- and N-Channel Power MOSFET Support
Programmable 1, 3, 10, 30 µA and 20 mA Drive Strengths
Phase Shift, Multiply/Divide, and Delay Capabilities
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz
Fusion Family
CoreMP7
Cortex-M1
CoreMP7
Cortex-M1
System Gates
Tiles (D-flip-flops)
Secure (AES) ISP
PLLs
Globals
Flash Memory Blocks (2 Mbits)
Total Flash Memory Bits
FlashROM Bits
RAM Blocks (4,608 bits)
RAM kbits
Analog Quads
Analog Input Channels
Gate Driver Outputs
I/O Banks (+ JTAG)
Maximum Digital I/Os
Analog I/Os
datasheet for more information.
product brief for more information.
®
Programmable System Chips
1
2
AFS090
90,000
2,304
2 M
Yes
1 k
18
27
15
20
75
1
1
6
5
5
4
Low Power Consumption
In-System Programming (ISP) and Security
Advanced Digital I/O
SRAMs and FIFOs
Soft ARM7™ Core Support in M7 and M1 Fusion
Devices
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
Sleep and Standby Low Power Modes
Secure ISP with 128-Bit AES via JTAG
FlashLock
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /1.8 V /
Differential I/O Standards: LVPECL, LVDS, BLVDS, and M-LVDS
Hot-Swappable I/Os
Programmable Output Slew Rate, Drive Strength, and Weak
Pull-Up/Down Resistor
Pin-Compatible Packages across the Fusion Family
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9,
and ×18 organizations available)
True Dual-Port SRAM (except ×18)
Programmable Embedded FIFO Control Logic
ARM Cortex™-M1 (without debug), CoreMP7Sd (with debug)
and CoreMP7S (without debug) )
1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
®
Built-In I/O Registers
700 Mbps DDR Operation
Support
M1AFS250
®
AFS250
250,000
6,144
to Secure FPGA Contents
2 M
114
Yes
1 k
18
36
18
24
1
1
8
6
6
4
See the Actel website for the latest version of the datasheet.
M7AFS600
M1AFS600
AFS600
600,000
13,824
4 M
108
172
Yes
1 k
18
24
10
30
10
40
2
2
5
A d v a n c e d v 1 . 4
M1AFS1500
1,500,000
AFS1500
38,400
8 M
270
252
Yes
1 k
18
60
10
30
10
40
2
4
5
®
i

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