afs600 Actel Corporation, afs600 Datasheet - Page 219

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

ATRTNx
AT returns are the returns for the temperature sensors.
The cathode terminal of the external diodes should be
connected to these pins. There is one analog return pin
for every two Analog Quads. The x in the ATRTNx
designator indicates the quad pairing (x = 0 for AQ1 and
AQ2, x = 1 for AQ2 and AQ3, ..., x = 4 for AQ8 and AQ9).
The signals that drive these pins are called out as
ATRETUNxy in the software (where x and y refer to the
quads that share the return signal). ATRTN is internally
connected to ground. It can be left floating when it is
unused.
GL
GL I/Os have access to certain clock conditioning circuitry
(and the PLL) and/or have direct access to the global
network (spines). Additionally, the global I/Os can be
used as Pro I/Os since they have identical capabilities.
Unused GL pins are configured as inputs with pull-up
resistors. See more detailed descriptions of global I/O
connectivity in the
on page
Refer to the
page 2-142
JTAG Pins
Fusion devices have a separate bank for the dedicated
JTAG pins. The JTAG pins can be run at any voltage from
1.5 V to 3.3 V (nominal). V
the JTAG state machine to operate, even if the device is
in bypass mode; V
and V
JTAG signals to transition the Fusion device.
Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility with supply selection and
simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned to be used, the
V
GND.
TCK
Test clock input for JTAG boundary scan, ISP, and UJTAG.
The TCK pin does not have an internal pull-up/-down
resistor. If JTAG is not used, Actel recommends tying off
TCK to GND or V
the FPGA pin. This prevents JTAG operation in case TMS
enters an undesired state.
JTAG
CC
pin together with the TRST pin could be tied to
2-22.
to the Fusion part must be supplied to allow
for a description of naming of global pins.
"User I/O Naming Convention" section on
JTAG
Temperature Monitor Return
Globals
Test Clock
JTAG
"Clock Conditioning Circuits" section
through a resistor placed close to
alone is insufficient. Both V
CC
must also be powered for
A d v an c ed v1 . 4
JTAG
Note that to operate at all V
will satisfy the requirements. Refer to
more information.
Table 2-180 • Recommended Tie-Off Values for the TCK and
TDI
Serial input for JTAG boundary scan, ISP, and UJTAG
usage. There is an internal weak pull-up resistor on the
TDI pin.
TDO
Serial output for JTAG boundary scan, ISP, and UJTAG
usage.
TMS
The TMS pin controls the use of the IEEE1532 boundary
scan pins (TCK, TDI, TDO, TRST). There is an internal weak
pull-up resistor on the TMS pin.
TRST
The TRST pin functions as an active low input to
asynchronously initialize (or reset) the boundary scan
circuitry. There is an internal weak pull-up resistor on the
TRST pin. If JTAG is not used, an external pull-down
resistor could be included to ensure the TAP is held in
reset mode. The resistor values must be chosen from
Table 2-180
requirement. The values in
resistor recommended when a single device is used and
to the equivalent parallel resistor when multiple devices
are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could
allow entering an undesired JTAG state. In such cases,
Actel recommends tying off TRST to GND through a
resistor placed close to the FPGA pin.
Note that to operate at all V
will satisfy the requirements.
V
V
V
V
V
Notes:
1. Equivalent parallel resistance if more than one device is on
2. The TCK pin can be pulled up/down.
3. The TRST pin can only be pulled down.
JTAG
JTAG
JTAG
JTAG
JTAG
JTAG chain.
at 3.3 V
at 2.5 V
at 1.8 V
at 1.5 V
and must satisfy the parallel resistance value
TRST Pins
Actel Fusion Programmable System Chips
Test Data Input
Test Data Output
Test Mode Select
Boundary Scan Reset Pin
Table 2-180
Tie-Off Resistance
JTAG
JTAG
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
voltages, 500 Ω to 1 kΩ
voltages, 500 Ω to 1 kΩ
correspond to the
Table 2-180
2, 3
2-205
for