afs600 Actel Corporation, afs600 Datasheet - Page 81

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

The following signals are used to configure the FIFO4K18
memory element:
WW and RW
These signals enable the FIFO to be configured in one of
the five allowable aspect ratios
Table 2-33 • Aspect Ratio Settings for WW[2:0]
WBLK and RBLK
These signals are active low and will enable the
respective ports when LOW. When the RBLK signal is
HIGH, the corresponding port’s outputs hold the
previous value.
WEN and REN
Read and write enables. WEN is active low and REN is
active high by default. These signals can be configured as
active high or low.
WCLK and RCLK
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
RPIPE
This signal is used to specify pipelined read on the
output. A LOW on RPIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
RESET
This active low signal resets the output to zero when
asserted. It resets the FIFO counters. It also sets all the RD
pins LOW, the FULL and AFULL pins LOW, and the EMPTY
and AEMPTY pins HIGH
Table 2-34 • Input Data Signal Usage for Different Aspect
WW2, WW1, WW0
000
001
010
011
100
101, 110, 111
D×W
4k
2k
1k
512
256
×
×
×
×
×
1
2
4
9
18
Ratios
RW2, RW1, RW0
(Table
101, 110, 111
000
001
010
011
100
2-34).
(Table
WD[17:1], RD[17:1]
WD[17:2], RD[17:2]
WD[17:4], RD[17:4]
WD[17:9], RD[17:9]
WD/RD Unused
2-33).
–
Reserved
256
512
D
4k
2k
1k
×
×
×
×
×
W
×
1
2
4
18
9
A d v an c ed v1 . 4
WD
This is the input data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. When a data width
less than 18 is specified, unused higher-order signals
must be grounded
RD
This is the output data bus and is 18 bits wide. Not all 18
bits are valid in all configurations. Like the WD bus, high-
order bits become unusable if the data width is less than
18. The output data on unused pins is undefined
(Table
ESTOP, FSTOP
ESTOP is used to stop the FIFO read counter from further
counting once the FIFO is empty (i.e., the EMPTY flag
goes HIGH). A HIGH on this signal inhibits the counting.
FSTOP is used to stop the FIFO write counter from further
counting once the FIFO is full (i.e., the FULL flag goes
HIGH). A HIGH on this signal inhibits the counting.
For more information on these signals, refer to the
"ESTOP and FSTOP Usage" section on page
FULL, EMPTY
When the FIFO is full and no more data can be written,
the FULL flag asserts HIGH. The FULL flag is synchronous
to WCLK to inhibit writing immediately upon detection
of a full condition and to prevent overflows. Since the
write address is compared to a resynchronized (and thus
time-delayed) version of the read address, the FULL flag
will remain asserted until two WCLK active edges after a
read operation eliminates the full condition.
When the FIFO is empty and no more data can be read,
the EMPTY flag asserts HIGH. The EMPTY flag is
synchronous to RCLK to inhibit reading immediately
upon detection of an empty condition and to prevent
underflows. Since the read address is compared to a
resynchronized (and thus time-delayed) version of the
write address, the EMPTY flag will remain asserted until
two RCLK active edges after a write operation removes
the empty condition.
For more information on these signals, refer to the
Flag Usage Considerations" section on page
AFULL, AEMPTY
These are programmable flags and will be asserted on
the
respectively.
When the number of words stored in the FIFO reaches
the amount specified by AEVAL while reading, the
AEMPTY output will go HIGH. Likewise, when the
number of words stored in the FIFO reaches the amount
specified by AFVAL while writing, the AFULL output will
go HIGH.
threshold
2-34).
Actel Fusion Programmable System Chips
specified
(Table
2-34).
by
AFVAL
and
2-68.
2-68.
AEVAL,
"FIFO
2-67