afs600 Actel Corporation, afs600 Datasheet - Page 69

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

The following signals are used to configure the RAM4K9
memory element:
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of
four allowable aspect ratios
Table 2-27 • Allowable Aspect Ratio Settings for
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, the corresponding port’s outputs hold the
previous value.
WENA and WENB
These signals switch the RAM between read and write
mode for the respective ports. A LOW on these signals
indicates a write operation, and a HIGH indicates a read.
CLKA and CLKB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
PIPEA and PIPEB
These signals are used to specify pipelined read on the
output. A LOW on PIPEA or PIPEB indicates a
nonpipelined read, and the data appears on the
corresponding output in the same clock cycle. A HIGH
indicates a pipelined, read and data appears on the
corresponding output in the next clock cycle.
WMODEA and WMODEB
These signals are used to configure the behavior of the
output when the RAM is in write mode. A LOW on these
signals makes the output retain data from the previous
read. A HIGH indicates pass-through behavior, wherein
the data being written will appear immediately on the
output. This signal is overridden when the RAM is being
read.
WIDTHA1, WIDTHA0
00
01
10
11
Note: The aspect ratio settings are constant and cannot be
changed on the fly.
WIDTHA[1:0]
WIDTHB1, WIDTHB0
(Table
00
01
10
11
2-27).
512×9
D×W
4k×1
2k×2
1k×4
A d v an c ed v1 . 4
RESET
This active low signal resets the output to zero, disables
reads and writes from the SRAM block, and clears the
data hold registers when asserted. It does not reset the
contents of the memory.
ADDRA and ADDRB
These are used as read or write addresses, and they are 12
bits wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded
Table 2-28 • Address Pins Unused/Used for Various
DINA and DINB
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded
DOUTA and DOUTB
These are the nine-bit output data signals. Not all nine
bits are valid in all configurations. As with DINA and
DINB, high-order bits may not be used
output data on unused pins is undefined.
Table 2-29 • Unused/Used Input and Output Data Pins for
D×W
4k×1
2k×2
1k×4
512×9
Note: The "x" in ADDRx implies A or B.
D×W
4k×1
2k×2
1k×4
512×9
Note: The "x" in DINx and DOUTx implies A or B.
Supported Bus Widths
Various Supported Bus Widths
Actel Fusion Programmable System Chips
Unused
Unused
[11:10]
[11:9]
None
None
[8:1]
[8:2]
[8:4]
[11]
DINx/DOUTx
ADDRx
(Table
(Table
(Table
Used
[11:0]
[10:0]
Used
[9:0]
[8:0]
[1:0]
[3:0]
[8:0]
2-29).
[0]
2-29). The
2-28).
2-55