afs600 Actel Corporation, afs600 Datasheet - Page 46

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Real-Time Counter
The RTC can be configured to power up the FPGA fabric
at a specific time or periodically. Custom user logic or a
soft microcontroller within the FPGA fabric portion of
the Fusion device can be programmed to read and
modify the registers in the RTC. Based on this
information or other internal or external conditions, the
FPGA may decide to power down the voltage regulator
and thereby shut off the FPGA fabric.
The 3.3 V supply must be valid and the crystal oscillator
(nominally 32.768 kHz) enabled for a self-timed wake-
up/restart operation. When operating from the 3.3 V
supply with the 1.5 V core voltage disabled, the ACM
interface to the FPGA is disabled.
A 40-bit loadable counter is used as the primary
timekeeping element within the RTC. This counter can be
configured to reset itself when a count value is reached
that matches the value set within a 40-bit match register.
Note that the only exception to this self-clearing
mechanism occurs when the 40-bit counter is equal to
zero (0x0000000000), since the counter would never
increment from zero. When the device is first powered
up (i.e., when the 3.3 V supply becomes valid), the 40-bit
counter and 40-bit match register are cleared to logic 0,
and the MATCH output signal is active (logic 1). At any
time when the 40-bit counter value does not match the
value in the 40-bit match register, the MATCH output
signal will become inactive (logic 0).
Both the counter and match registers are addressable
(read/write) from the FPGA and through a JTAG
instruction. The RTC is considered part of the analog
system and is accessed via the ACM. Refer to the
Configuration MUX (ACM)" section on page 2-111
detailed instructions on writing to the RTC via the ACM.
The counter action can be suspended/resumed by
clearing/setting the Cntr_En bit in the Control/Status
register.
If a 32.768 kHz external crystal is connected to the crystal
oscillator pad, the 40-bit counter will have a maximum
count of 4,294,967,296 seconds, which equates to just
Table 2-15 • RTC Macro Signal Description
2 -3 2
Signal Name
RTCMATCH
RTCPSMMATCH
RTCXTLMODE[1:0]
RTCXTLSEL
RTCCLK
Actel Fusion Programmable System Chips
Number of Bits
1
1
1
2
1
Direction
"Analog
Out
Out
Out
Out
In
A d v a n c e d v 1 . 4
for
over 136 years of elapsed timekeeping with a minimum
period of 1/256 of a second, which will be the toggle rate
of the LSB of the 40-bit counter.
Frequencies other than 32.768 kHz can be used as a clock
source with the appropriate scaling of the LSB time
interval. The maximum input clock frequency is 20 MHz
(the crystal oscillator limit).
The RTC signals are included in the Analog Block macro.
The signal functions and descriptions are listed in
Table
A Fusion use model includes the RTC controlling the
power-up state of the FPGA core via the 1.5 V regulator.
To support this model, the crystal oscillator must be
running and configured when the FPGA is powered off.
Hence, when the RTC is enabled in the system design, it
will
RTCXTLMODE[1:0] and RTCXTLSEL pins.
A 7-bit prescaler block is used to divide the source clock
(from the external crystal) by 128. This prescaled 50%-
duty-cycle clock signal is then used by the counter logic
as its reference clock. Given an external crystal frequency
of 32.768 kHz, the prescaler output clock will toggle at a
rate of 32.768 kHz / 128 = 256 Hz.
The RTC is built from and controlled by a set of registers,
denoted "Main Registers" in
These registers are accessed via the ACM.
The FPGA fabric portion of the Fusion device must be
powered up and active at least once to write to the
various registers within the RTC to initialize them for the
user’s application. Users set up the RTC by configuring it
from the Actel SmartGen tool, implementing custom
logic or programming a soft microcontroller.
The 40-bit counter and match registers are each divided
into five bytes. Each byte is directly addressable by the
ACM. The address map of registers accessed through the
ACM and used by the RTC is shown in
page
Match between 40-bit counter and match register
RTCMATCH connected to voltage regulator power supply
monitor (VRPSM)
Drives XTLOSC RTCMODE[1:0] pins
Drives XTLOSC SELMODE pin
RTC clock input from XTLOSC CLKOUT pin
2-33.
2-15.
configure
(Figure 2-30 on page
the
Function
crystal
Figure 2-27 on page
2-36)
oscillator
Table 2-16 on
via
2-31.
the