afs600 Actel Corporation, afs600 Datasheet - Page 25

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Global Resources (VersaNets)
Fusion devices offer powerful and flexible control of
circuit timing through the use of analog circuitry. Each
chip has six CCCs. The west CCC also contains a PLL core.
In the two larger devices (AFS600 and AFS1500), the west
and the east CCCs each contain a PLL. The PLLs include
delay lines, a phase shifter (0°, 90°, 180°, 270°), and clock
multipliers/dividers. Each CCC has all the circuitry needed
for the selection and interconnection of inputs to the
VersaNet global network. The east and west CCCs each
have access to three VersaNet global lines on each side of
the chip (six lines total). The CCCs at the four corners
each have access to three quadrant global lines on each
quadrant of the chip.
Advantages of the VersaNet Approach
One of the architectural benefits of Fusion is the set of
powerful and low-delay VersaNet global networks. Fusion
offers six chip (main) global networks that are distributed
from the center of the FPGA array
Figure 2-11 • Overview of Fusion VersaNet Global Network
Global Pads
Chip (main)
Spine-Selection
Bottom Spine
Quadrant Global Pads
Tree MUX
Top Spine
(Figure
2-11). In
Pad Ring
A d v an c ed v1 . 4
addition, Fusion devices have three regional globals
(quadrant globals) in each of the four chip quadrants. Each
core VersaTile has access to nine global network resources:
three quadrant and six chip (main) global networks. There
are a total of 18 global networks on the device. Each of
these networks contains spines and ribs that reach all
VersaTiles in all quadrants
flexible VersaNet global network architecture allows users
to map up to 180 different internal/external clocks in a
Fusion device. Details on the VersaNet networks are given
in
VersaNet global network allows the designer to address
several design requirements. User applications that are
clock-resource-intensive can easily route external or gated
internal clocks using VersaNet global routing networks.
Designers can also drastically reduce delay penalties and
minimize resource usage by mapping critical, high-fanout
nets to the VersaNet global network.
Table 2-4 on page
Actel Fusion Programmable System Chips
High-Performance
VersaNet Global Network
2-12. The flexibility of the Fusion
(Figure 2-12 on page
Global Ribs
Global Spine
Main (chip)
Global Network
Global
Pads
2-12). This
2-11