afs600 Actel Corporation, afs600 Datasheet - Page 107

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

The speed of the ADC depends on its internal clock,
ADCCLK, which is not accessible to users. The ADCCLK is
derived from SYSCLK. Input signal TVC[7:0], Time Divider
Control, determines the speed of the ADCCLK in
relationship to SYSCLK, based on
Table 2-42 • TVC Bits Function
The frequency of ADCCLK, f
to 10 MHz.
The inputs to the ADC are synchronized to SYSCLK. A
conversion is initiated by asserting the ADCSTART signal
on a rising edge of SYSCLK.
Figure 2-83 on page 2-97
the ADC.
A conversion is performed in three phases. In the first
phase, the analog input voltage is sampled on the input
capacitor. This phase is called sample phase. During the
sample phase, the output signals BUSY and SAMPLE
change from '0' to '1', indicating the ADC is busy and
sampling the analog signal. The sample time can be
controlled by input signals STC[7:0]. The sample time can
be calculated by
time for the ADC along with the use of Prescaler or
Current Monitor or Temperature Monitor, the minimum
sample time for each must be obeyed. Refer to the
corresponding
information.
Table 2-43 • STC Bits Function
Sample time is computed based on the period of
ADCCLK.
The second phase is called the distribution phase. During
distribution phase, the ADC computes the equivalent
digital value from the value stored in the input capacitor.
Name
TVC
Name
STC
TVC: Time Divider Control (0–255)
t
between 0.5 MHz and 10 MHz
t
STC: Sample Time Control value (0–255)
t
ADCCLK
SYSCLK
SAMPLE
t
is the period of SYSCLK
Bits
[7:0]
ADCCLK
is the sample time
is the period of ADCCLK, and must be
t
sample
section
EQ
=
2-11. When controlling the sample
=
4
Sample time control
(
×
Bits
[7:0]
2
and
(
show the timing diagram for
+
1
ADCCLK
Figure 2-82 on page 2-96
STC
+
TVC
) t
Table 2-43
×
EQ
, must be within 0.5 Hz
)
Function
SYSCLK divider control
ADCCLK
×
2-10.
t
SYSCLK
Function
for
EQ 2-10
further
EQ 2-11
A d v an c ed v1 . 4
and
In this phase, the output signal SAMPLE goes back to '0',
indicating the sample is completed; but the BUSY signal
remains '1', indicating the ADC is still busy for
distribution. The distribution time depends strictly on the
number of bits. If the ADC is configured as a 10-bit ADC,
then 10 ADCCLK cycles are needed.
distribution time.
The last phase is the post-calibration phase. This is an
optional phase. The post-calibration phase takes two
ADCCLK cycles. The output BUSY signal will remain '1'
until the post-calibration phase is completed. If the post-
calibration phase is skipped, then the BUSY signal goes
to '0' after distribution phase. As soon as BUSY signal
goes to '0', the DATAVALID signal goes to '1', indicating
the digital result is available on the RESULT output
signals. DATAVAILD will remain '1' until the next
ADCSTART is asserted. Actel recommends enabling post-
calibration to compensate for drift and temperature-
dependent effects. This ensures that the ADC remains
consistent over time and with temperature. The post-
calibration phase is enabled by bit 3 of the Mode
register.
MODE[3]: Bit 3 of the Mode register, described in
Table 2-41 on page
The calculation for the conversion time for the ADC is
summarized in
t
conv
N: Number of bits
t
t
synchronize
purposes, the worst case is a period of SYSCLK,
t
t
t
t
t
synchronize
purposes, the worst case is a period of SYSCLK,
t
conv
sync_read
SYSCLK
sample
distrib
post-cal
sync_write
SYSCLK
= t
EQ 2-13
sync_read
: conversion time
: Distribution time
t
: Sample time
.
.
post-cal
: Post-calibration time
:
EQ
Actel Fusion Programmable System Chips
:
describes the post-calibration time.
maximum
+ t
Maximum
2-14.
t
2-92.
=
distrib
sample
with
with
MODE 3 [ ]
=
+ t
N t
SYSCLK.
SYSCLK.
×
distrib
time
×
time
ADCCLK
(
2 t
+ t
×
EQ 2-12
post-cal
ADCCLK
for
for
For
For
a
a
)
+ t
describes the
sync_write
calculation
calculation
signal
signal
EQ 2-12
EQ 2-13
EQ 2-14
2-93
to
to