afs600 Actel Corporation, afs600 Datasheet - Page 12

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Embedded Memories
Flash Memory Blocks
The flash memory available in each Fusion device is
composed of one to four flash blocks, each 2 Mbits in
density. Each block operates independently with a
dedicated flash controller and interface. Fusion flash
memory blocks combine fast access times (60 ns random
access and 10 ns access in Read-Ahead mode) with a
configurable 8-, 16-, or 32-bit datapath, enabling high-
speed flash operation without wait states. The memory
block is organized in pages and sectors. Each page has 128
bytes, with 33 pages comprising one sector and 64 sectors
per block. The flash block can support multiple partitions.
The only constraint on size is that partition boundaries
must coincide with page boundaries. The flexibility and
granularity enable many use models and allow added
granularity in programming updates.
Fusion devices support two methods of external access to
the flash memory blocks. The first method is a serial
interface that features a built-in JTAG-compliant port,
which allows in-system programmability during user or
monitor/test
programming of an AES-encrypted stream. Secure data
can be passed through the JTAG interface, decrypted, and
then programmed in the flash block. The second method
is a soft parallel interface.
FPGA logic or an on-chip soft microprocessor can access
flash memory through the parallel interface. Since the
flash parallel interface is implemented in the FPGA fabric,
it can potentially be customized to meet special user
requirements. For more information, refer to the
Handbook.
configurable byte-wide (×8), word-wide (×16), or dual-
word-wide (×32) data port options. Through the
programmable flash parallel interface, the on-chip and
off-chip memories can be cascaded for wider or deeper
configurations.
The flash memory has built-in security. The user can
configure either the entire flash block or the small blocks
to prevent unintentional or intrusive attempts to change
or destroy the storage contents. Each on-chip flash
memory block has a dedicated controller, enabling each
block to operate independently.
The flash block logic consists of the following sub-blocks:
1 -6
Actel Fusion Programmable System Chips
• Flash block – Contains all stored data. The flash
• Page Buffer – Contains the contents of the current
• Block Buffer – Contains the contents of the last
block contains 64 sectors and each sector contains
33 pages of data.
page being modified. A page contains 8 blocks of
data.
block accessed. A block contains 128 data bits.
The flash memory parallel interface provides
modes.
This
serial
interface
supports
CoreCFI
A d v a n c e d v 1 .4
User Nonvolatile FlashROM
In addition to the flash blocks, Actel Fusion devices have
1 kbit of user-accessible, nonvolatile FlashROM on-chip.
The FlashROM is organized as 8×128-bit pages. The
FlashROM can be used in diverse system applications:
The FlashROM is written using the standard IEEE 1532
JTAG programming interface. Pages can be individually
programmed
decryption can be used selectively over public networks
to securely load data such as security keys stored in the
FlashROM for a user design.
The FlashROM can be programmed (erased and written)
via the JTAG programming interface, and its contents
can be read back either through the JTAG programming
interface or via direct FPGA core addressing.
The FlashPoint tool in the Actel Fusion development
software solutions, Libero IDE and Designer, has
extensive
FlashROM. One such feature is auto-generation of
sequential programming files for applications requiring
a unique serial number in each part. Another feature
allows the inclusion of static data for system version
control. Data for the FlashROM can be generated quickly
and easily using the Actel Libero IDE and Designer
software
support is also included to allow for easy programming
of large numbers of parts with differing FlashROM
contents.
SRAM and FIFO
Fusion devices have embedded SRAM blocks along the
north and south sides of the device. Each variable-aspect-
ratio SRAM block is 4,608 bits in size. Available memory
configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1
bits. The individual blocks have independent read and
write ports that can be configured with different bit
• ECC Logic – The flash memory stores error
• Internet protocol addressing (wireless or fixed)
• System calibration settings
• Device serialization and/or inventory control
• Subscription-based business models (for example,
• Secure key storage for secure communications
• Asset management/tracking
• Date stamping
• Version management
correction information with each block to perform
single-bit error correction and double-bit error
detection on all data blocks.
set-top boxes)
algorithms
tools.
support
(erased
Comprehensive
for
and
flash
written).
memory
programming
On-chip
blocks
AES
and
file