afs600 Actel Corporation, afs600 Datasheet - Page 220

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Special Function Pins
NC
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
DC
This pin should not be connected to any signals on the
PCB. These pins should be left unconnected.
NCAP
Negative Capacitor is where the negative terminal of the
charge pump capacitor is connected. A capacitor, with a
2.2 µF recommended value, is required to connect
between PCAP and NCAP.
PCAP
Positive Capacitor is where the positive terminal of the
charge pump capacitor is connected. A capacitor, with a
2.2 µF recommended value, is required to connect
between PCAP and NCAP.
PUB
Push button is the connection for the external
momentary switch used to turn on the 1.5 V voltage
regulator and can be floating if not used.
PTBASE
Pass Transistor Base is the control signal of the voltage
regulator. This pin should be connected to the base of
the external pass transistor used with the 1.5 V internal
voltage regulator and can be floating if not used.
PTEM
Pass Transistor Emitter is the feedback input of the
voltage regulator.
This pin should be connected to the emitter of the
external pass transistor used with the 1.5 V internal
voltage regulator and can be floating if not used.
XTAL1
Input to crystal oscillator circuit. Pin for connecting
external crystal, ceramic resonator, RC network, or
external clock input. When using an external crystal or
ceramic
recommended (Please refer to the crystal oscillator
manufacturer for proper capacitor value).
If using external RC network or clock input, XTAL1
should be used and XTAL2 left unconnected.
XTAL2
Input to crystal oscillator circuit. Pin for connecting
external crystal, ceramic resonator, RC network, or
external clock input. When using an external crystal or
ceramic
2 -2 0 6
Actel Fusion Programmable System Chips
oscillator,
oscillator,
No Connect
Don't Connect
Negative Capacitor
Positive Capacitor
Push Button
Pass Transistor Base
Pass Transistor Emitter
Crystal Oscillator Circuit Input
Crystal Oscillator Circuit Input
external
external
capacitors
capacitors
are
are
A d v a n c e d v 1 . 4
also
also
recommended (Please refer to the crystal oscillator
manufacturer for proper capacitor value).
If using external RC network or clock input, XTAL1
should be used and XTAL2 left unconnected.
Software Tools and Programming
Overview of Tools Flow
The Fusion family of FPGAs is fully supported by both
Actel Libero IDE and Designer FPGA development
software. Actel Libero IDE is an integrated design
manager that seamlessly integrates design tools while
guiding the user through the design flow, managing all
design and log files, and passing necessary design data
among tools. Additionally, Libero IDE allows users to
integrate both schematic and HDL synthesis into a single
flow and verify the entire design in a single environment
(see the
website). Libero IDE includes Synplify
Synplicity,
ModelSim
WaveFormer Lite™ AE from SynaptiCAD,
Physical Synthesis from Magma Design Automation,™
and Designer software from Actel.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
the following:
With the Designer software, a user can lock the design
pins before layout while minimally impacting the results
of
annotation flow is compatible with all major simulators.
Included in the Designer software is SmartGen core
generator, which easily creates commonly used logic
functions for implementation into your Fusion-based
schematic or HDL design.
• SmartTime – a world-class integrated static timing
• NetlistViewer – a design netlist schematic viewer
• ChipPlanner – a graphical floorplanning viewer
• SmartPower – a sophisticated power analysis
• PinEditor – a graphical application for editing pin
• I/O Attribute Editor – displays all assigned and
place-and-route.
analyzer and constraints editor that supports
timing-driven place-and-route
and editor
environment that gives designers the ability to
quickly determine the power consumption of an
FPGA or its components
assignments and I/O attributes
unassigned I/O macros and their attributes in a
spreadsheet format
Libero IDE flow diagram
®
®
ViewDraw
HDL Simulator from Mentor Graphics,
®
Additionally,
AE from Mentor Graphics,
located on the Actel
the
®
®
PALACE™ AE
Actel
AE from
back-
®