afs600 Actel Corporation, afs600 Datasheet - Page 22

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Routing Architecture
The routing structure of Fusion devices is designed to
provide high performance through a flexible four-level
hierarchy of routing resources: ultra-fast local resources;
efficient long-line resources; high-speed very-long-line
resources; and the high-performance VersaNet networks.
The ultra-fast local resources are dedicated lines that allow
the output of each VersaTile to connect directly to every
input of the eight surrounding VersaTiles
exception to this is that the SET/CLR input of a VersaTile
configured as a D-flip-flop is driven only by the VersaNet
global network.
The efficient long-line resources provide routing for
longer distances and higher-fanout connections. These
resources vary in length (spanning one, two, or four
VersaTiles), run both vertically and horizontally, and
cover the entire Fusion device
Each VersaTile can drive signals onto the efficient long-
line resources, which can access every input of every
VersaTile. Active buffers are inserted automatically by
routing software to limit loading effects.
Note: Input to the core cell for the D-flip-flop set and reset is only available via the VersaNet global network connection.
Figure 2-8 •
2 -8
Actel Fusion Programmable System Chips
Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
L
L
L
(Figure 2-9 on page
Inputs
(Figure
L
L
L
2-8). The
A d v a n c e d v 1 .4
2-9).
Long Lines
The high-speed very-long-line resources, which span the
entire device with minimal delay, are used to route very
long or high-fanout nets: length +/–12 VersaTiles in the
vertical direction and length +/–16 in the horizontal
direction from a given core VersaTile
page
ProASIC3 devices, have been enhanced. This provides a
significant performance boost for long-reach signals.
The high-performance VersaNet global networks are low-
skew, high-fanout nets that are accessible from external
pins or from internal logic
These nets are typically used to distribute clocks, reset
signals, and other high-fanout nets requiring minimum
skew. The VersaNet networks are implemented as clock
trees, and signals can be introduced at any junction. These
can be employed hierarchically, with signals accessing
every input on all VersaTiles.
L
L
L
2-10). Very long lines in Fusion devices, like those in
Ultra-Fast Local Lines
(connects a VersaTile to the
adjacent VersaTile, I/O buffer,
or memory block)
(Figure 2-11 on page
(Figure 2-10 on
2-11).