afs600 Actel Corporation, afs600 Datasheet - Page 222

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

noninvasive instruction. Refer to the standard or the
System Programming (ISP) of Actel's Low-Power Flash
Devices Using FlashPro3
Boundary Scan
Fusion devices are compatible with IEEE Standard 1149.1,
which defines a hardware architecture and the set of
mechanisms for boundary scan testing. The basic Fusion
boundary scan logic circuit is composed of the test access
port (TAP) controller, test data registers, and instruction
register
supports all mandatory IEEE 1149.1 instructions (EXTEST,
SAMPLE/PRELOAD, and BYPASS) and the optional
IDCODE instruction
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-205
recommendations for TDO and TCK pins. The TAP
controller is a 4-bit state machine (16 states) that
operates as shown in
and 0s represent the values that must be present on TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
Table 2-181 • TRST and TCK Pull-Down Recommendations
2 -2 0 8
V
V
V
V
V
Note: *Equivalent parallel resistance if more than one device is
JTAG
JTAG
JTAG
JTAG
Actel Fusion Programmable System Chips
JTAG
at 3.3 V
at 2.5 V
at 1.8 V
at 1.5 V
on JTAG chain.
(Figure 2-138 on page
(Table 2-182 on page
Figure 2-138 on page
document for more details.
Tie-Off Resistance*
200 Ω to 1 kΩ
200 Ω to 1 kΩ
500 Ω to 1 kΩ
500 Ω to 1 kΩ
2-209). This circuit
for pull-up/-down
2-209).
2-209. The 1s
A d v a n c e d v 1 . 4
In-
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain HIGH for five TCK cycles. The TRST pin
can also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
Fusion devices support three types of test data registers:
bypass, device identification, and boundary scan. The
bypass register is selected when no other register needs
to be accessed in a device. This speeds up test data
transfer to other devices in a test data path. The 32-bit
device identification register is a shift register with four
fields (LSB, ID number, part number, and version). The
boundary scan register observes and controls the state of
each I/O pin. Each I/O cell has three boundary scan
register cells, each with a serial-in, serial-out, parallel-in,
and parallel-out pin.
The serial pins are used to serially connect all the
boundary scan register cells in a device into a boundary
scan register chain, which starts at the TDI pin and ends
at the TDO pin. The parallel ports are connected to the
internal core logic I/O tile and the input, output, and
control ports of an I/O buffer to capture and load data
into the register to control or observe the logic state of
each I/O.