afs600 Actel Corporation, afs600 Datasheet - Page 137

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to
representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in
implement single or differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input register 2 does not
have a CLR/PRE pin, as this register is used for DDR implementation. The I/O register combining must satisfy some
rules.
Note: Fusion I/Os have registers to support DDR functionality (see the
Figure 2-92 • I/O Block Logical Representation
From FPGA Core
information).
To FPGA Core
I/O / CLR or I/O / PRE / OCE
I/O / D1 / ICE
I/O / OCLK
I/O / ICLK
I/O / Q0
I/O / Q1
I/O / OE
I/O / D0
CLR/PRE
CLR/PRE
ICE
A d v an c ed v1 . 4
Input
Input
Reg
Reg
1
3
"Double Data Rate (DDR) Support" section on page 2-124
OCE
OCE
ICE
Output
Enable
Output
Output
Reg
Reg
Reg
6
4
5
CLR/PRE
CLR/PRE
CLR/PRE
Input
Reg
2
Actel Fusion Programmable System Chips
A
Figure
Y
Figure 2-92
2-92) between registers to
Resistor Control
Pull-Up/Down
E = Enable Pin
and Slew-Rate Control
Signal Drive Strength
PAD
for a simplified
for more
2-123