afs600 Actel Corporation, afs600 Datasheet - Page 156

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

User I/O Naming Convention
Due to the comprehensive and flexible nature of Fusion device user I/Os, a naming scheme is used to show the details
of the I/O
belongs, as well as the pairing and pin polarity for differential I/Os.
2 -1 4 2
I/O Nomenclature = Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
G
m
n
u
x
w
B
y
V
z
Actel Fusion Programmable System Chips
= Global
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east
= Global input MUX and pin number of the associated Global location m, either A0, A1, A2, B0, B1, B2, C0, C1, or
= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeding in a clockwise
= P (Positive) or N (Negative) for differential pairs, or R (Regular – single-ended) for the I/Os that support single-
= D (Differential Pair), P (Pair), or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded
= Bank
= Bank number (0–3). The Bank number starts at 0 from the northwest I/O bank and proceeds in a clockwise
= Reference voltage
= Minibank number
middle), D (southeast corner), E (southwest corner), and F (west middle).
C2.
direction.
ended and voltage-referenced I/O standards only. U (Positive-LVDS only) or V (Negative-LVDS only) restrict the
I/O differential pair from being selected as an LVPECL pair.
out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are
bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.
For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal
adjacency does not meet the requirements for a true differential pair.
direction.
(Figure 2-105 on page 2-143
Figure 2-22 on page 2-25
shows the three input pins per clock source MUX at CCC location m.
and
Figure 2-106 on page
A d v a n c e d v 1 . 4
2-143). The name identifies to which I/O bank it