afs600 Actel Corporation, afs600 Datasheet - Page 13

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

widths on each port. For example, data can be written
through a 4-bit port and read as a single bitstream. The
SRAM blocks can be initialized from the flash memory
blocks or via the device JTAG port (ROM emulation
mode), using the UJTAG macro.
In addition, every SRAM block has an embedded FIFO
control unit. The control unit allows the SRAM block to
be configured as a synchronous FIFO without using
additional core VersaTiles. The FIFO width and depth are
programmable. The FIFO also features programmable
Almost Empty (AEMPTY) and Almost Full (AFULL) flags in
addition to the normal EMPTY and FULL flags. The
embedded FIFO control unit contains the counters
necessary for the generation of the read and write
address pointers. The SRAM/FIFO blocks can be cascaded
to create larger configurations.
Clock Resources
PLLs and Clock Conditioning Circuits (CCCs)
Fusion devices provide designers with very flexible clock
conditioning capabilities. Each member of the Fusion
family contains six CCCs. In the two larger family
members, two of these CCCs also include a PLL; the
smaller devices support one PLL.
The inputs of the CCC blocks are accessible from the
FPGA core or from one of several inputs with dedicated
CCC block connections.
The CCC block has the following key features:
Additional CCC specifications:
• Wide input frequency range (f
• Output frequency range (f
• Clock phase adjustment via programmable and
• Clock skew minimization (PLL)
• Clock frequency synthesis (PLL)
• On-chip analog clocking resources usable as
• Internal phase shift = 0°, 90°, 180°, and 270°
• Output duty cycle = 50% ± 1.5%
• Low output jitter. Samples of peak-to-peak period
• Maximum acquisition time = 150 µs
• Low power consumption of 5 mW
350 MHz
350 MHz
fixed delays from –6.275 ns to +8.75 ns
inputs:
– 100 MHz on-chip RC oscillator
– Crystal oscillator
jitter when a single global network is used:
– 70 ps at 350 MHz
– 90 ps at 100 MHz
– 180 ps at 24 MHz
– Worst case < 2.5% × clock period
OUT_CCC
IN_CCC
) = 0.75 MHz to
) = 1.5 MHz to
A d v an c ed v1 . 4
Global Clocking
Fusion devices have extensive support for multiple
clocking domains. In addition to the CCC and PLL support
described above, there are on-chip oscillators as well as a
comprehensive global clock distribution network.
The integrated RC oscillator generates a 100 MHz clock.
It is used internally to provide a known clock source to
the flash memory read and write control. It can also be
used as a source for the PLLs.
The crystal oscillator supports the following operating
modes:
Each VersaTile input and output port has access to nine
VersaNets: six main and three quadrant global networks.
The VersaNets can be driven by the CCC or directly
accessed from the core via MUXes. The VersaNets can be
used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
Digital I/Os with Advanced I/O Standards
The Fusion family of FPGAs features a flexible digital I/O
structure, supporting a range of voltages (1.5 V, 1.8 V,
2.5 V, and 3.3 V). Fusion FPGAs support many different
digital I/O standards, both single-ended and differential.
The I/Os are organized into banks, with four or five banks
per device. The configuration of these banks determines
the I/O standards supported. The banks along the east
and west sides of the device support the full range of I/O
standards (single-ended and differential). The south bank
supports the Analog Quads (analog I/O). In the family's
two smaller devices, the north bank supports multiple
single-ended digital I/O standards. In the family’s larger
devices, the north bank is divided into two banks of
digital Pro I/Os, supporting a wide variety of single-
ended, differential, and voltage-referenced I/O standards.
Each I/O module contains several input, output, and enable
registers. These registers allow the implementation of the
following applications:
• Single-Data-Rate (SDR) applications
• Double-Data-Rate (DDR) applications—DDR LVDS I/O
• Fusion banks support LVPECL, LVDS, BLVDS, and M-LVDS
• Crystal (32.768 kHz to 20 MHz)
• Ceramic (500 kHz to 8 MHz)
• RC (32.768 kHz to 4 MHz)
for chip-to-chip communications
with 20 multi-drop points.
Actel Fusion Programmable System Chips
1-7