afs600 Actel Corporation, afs600 Datasheet - Page 109

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Integrated Voltage Reference
The Fusion device has an integrated on-chip 2.56 V
reference voltage for the ADC. The value of this
reference voltage was chosen to make the prescaling
and postscaling factors for the prescaler blocks change in
a binary fashion. However, if desired, an external
reference voltage of up to 3.3 V can be connected
between the VAREF and GNDREF pins. The VAREFSEL
control pin is used to select the reference voltage.
Table 2-44 • VAREF Bit Function
ADC Operation Description
The ADC can be powered down independently of the
FPGA core, as an additional control or for power-saving
considerations, via the PWRDWN pin of the Analog
Block. The PWRDWN pin controls only the comparators
in the ADC.
Once the ADC has powered up and been released from
reset, ADCRESET, the ADC will initiate a calibration
routine designed to provide optimal ADC performance.
The Fusion ADC offers a robust calibration scheme to
reduce integrated offset and linearity errors. The offset
and linearity errors of the main capacitor array are
compensated for with an 8-bit calibration capacitor
array. The offset/linearity error calibration is carried out
in two ways. First, a power-up calibration is carried out
when the ADC comes out of reset. This is initiated by the
CALIBRATE output of the Analog Block macro and is a
fixed number of ADC_CLK cycles (3,840 cycles), as shown
in
and offset errors of the capacitors are calibrated.
To further compensate for drift and temperature-
dependent effects, every conversion is followed by post-
calibration of either the offset or a bit of the main
capacitor array. The post-calibration ensures that, over
time and with temperature, the ADC remains consistent.
After both calibration and the setting of the appropriate
configurations, as explained above, the ADC is ready for
operation. Setting the ADCSTART signal high for one
clock period will initiate the sample and conversion of
the analog signal on the channel as configured by
CHNUMBER[4:0]. The status signals SAMPLE and BUSY
will show when the ADC is sampling and converting
(Figure 2-83 on page
initially go high. After the ADC has sampled and held the
analog signal, SAMPLE will go low. After the entire
operation has completed and the analog signal is
Name
VAREF
Figure 2-81 on page
Bit
0
Reference voltage selection
0 – Internal voltage reference selected. VAREF
pin outputs 2.56 V.
1 – Input external voltage reference from
VAREF and GNDREF
2-97). Both SAMPLE and BUSY will
2-96. In this mode, the linearity
Function
A d v an c ed v1 . 4
converted, BUSY will go low and DATAVALID will go
high. This indicates that the digital result is available on
the RESULT[11:0] pins.
DATAVALID will remain high until a subsequent
ADC_START is issued. The DATAVALID goes low on the
rising edge of SYSCLK as shown in
page
the ADC finishes the subsequent sample. The next
sampled RESULT will be available when DATAVALID goes
high again. It is ideal to read the RESULT when
DATAVALID is '1'. The RESULT is latched and remains
unchanged until the next DATAVLAID rising edge.
Intra-Conversion
Performing a conversion during power-up, calibration is
possible but should be avoided, since the performance is
not guaranteed, as shown in
This is described as intra-conversion.
Injected Conversion
A conversion can be interrupted by another conversion.
Before the current conversion is finished, a second
conversion can be started by issuing a pulse on signal
ADCSTART. When a second conversion is issued before
the current conversion is completed, the current
conversion would be dropped and the ADC would start
the second conversion on the rising edge of the SYSCLK.
This is known as injected conversion. Since the ADC is
synchronous, the minimum time to issue a second
conversion is two clock cycles of SYSCLK after the
previous one.
2-96. The RESULT signals will be kept constant until
Actel Fusion Programmable System Chips
Table 2-46 on page
Figure 2-82 on
2-102.
2-95