afs600 Actel Corporation, afs600 Datasheet - Page 221

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Actel Designer software is compatible with the most
popular FPGA design entry and verification tools from
EDA vendors, such as Cadence,
Graphics, Synopsys, and Synplicity. The Designer software
is available for both the Windows
systems.
CoreMP7 and Cortex-M1 Software Tools
CoreConsole is the Intellectual Property Deployment
Platform (IDP) that assists the developer in programming
the soft ARM core onto M7 (CoreMP7) and M1 (Cortex-M1)
Fusion
environment to work with the Libero IDE and Designer
FPGA development software tools concurrently.
Security
Fusion devices have a built-in 128-bit AES decryption
core. The decryption core facilitates secure, in-system
programming of the FPGA core array fabric and the
FlashROM. The FlashROM and the FPGA core fabric can
be
allowing the FlashROM to be updated without the need
for change to the FPGA core fabric. The AES master key is
stored in on-chip nonvolatile memory (flash). The AES
master key can be preloaded into parts in a secure
programming environment (such as the Actel in-house
programming center), and then "blank" parts can be
shipped to an untrusted programming or manufacturing
center for final personalization with an AES-encrypted
bitstream. Late stage product changes or personalization
can be implemented easily and securely by simply
sending a STAPL file with AES-encrypted data. Secure
remote field updates over public networks (such as the
Internet) are possible by sending and programming a
STAPL
information, refer to the
note.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-192) block cipher is the
National Institute of Standards and Technology (NIST)
replacement for DES (Data Encryption Standard FIPS46-
2). AES has been designed to protect sensitive
government information well into the 21st century. It
replaces the aging DES, which NIST adopted in 1977 as a
Federal Information Processing Standard used by federal
agencies to protect sensitive, unclassified information.
The 128-bit AES standard has 3.4 × 10
key variants, and it has been estimated that it would
take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in
Fusion
programming
authenticated by the part prior to programming to
programmed
devices.
file
devices
with
files
CoreConsole
in
independently
AES-encrypted
nonvolatile
sent
Fusion Security
to
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38
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A d v an c ed v1 . 4
All
be
ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of Fusion devices remain secure.
AES decryption can also be used on the 1,024-bit
FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support
for subscription model products. See the application
note
AES for Flash Memory
AES decryption can also be used on the flash memory
blocks. This allows for the secure update of the flash
memory blocks. During runtime, the encrypted data can
be clocked in via the JTAG interface. The data can be
passed through the internal AES decryption engine, and
the decrypted data can then be stored in the flash
memory block.
Programming
Programming
programming tools, such as Silicon Sculptor II (BP Micro
Systems) or FlashPro3 (Actel).
The user can generate STP programming files from the
Designer software and can use these files to program a
device.
Fusion devices can be programmed in-system. During
programming, V
internal 100 MHz oscillator. This oscillator is used as a
source for the 20 MHz oscillator that is used to drive the
charge pump for programming.
ISP
Fusion devices support IEEE 1532 ISP via JTAG and require
a single V
addition, programming via a microcontroller in a target
system can be achieved. Refer to the standard or the
System Programming (ISP) of Actel's Low-Power Flash
Devices Using FlashPro3
JTAG IEEE 1532
Programming with IEEE 1532
Fusion devices support the JTAG-based IEEE1532 standard
for ISP. As part of this support, when a Fusion device is in an
unprogrammed state, all user I/O pins are disabled. This is
achieved by keeping the global IO_EN signal deactivated,
which also has the effect of disabling the input buffers.
Consequently, the SAMPLE instruction will have no effect
while the Fusion device is in this unprogrammed state—
different behavior from that of the ProASIC
family. This is done because SAMPLE is defined in the
IEEE1532 specification as a noninvasive instruction. If the
input buffers were to be enabled by SAMPLE temporarily
turning on the I/Os, then it would not truly be a
Fusion Security
PUMP
Actel Fusion Programmable System Chips
voltage of 3.3 V during programming. In
can
CCOSC
for more details.
be
is needed in order to power the
document for more details.
performed
using
PLUS®
various
device
2-207
In-