afs600 Actel Corporation, afs600 Datasheet - Page 240

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more accurate and
detailed power estimations, use the SmartPower tool in the Libero IDE software.
The power calculation methodology described below uses the following variables:
The calculation should be repeated for each clock domain defined in the design.
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
3 -1 6
Actel Fusion Programmable System Chips
• The number of PLLs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• The number of NVM blocks used in the design
• The number of Analog Quads used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
• Enable rates of output buffers—guidelines are provided for typical applications in
• Read rate and write rate to the RAM—guidelines are provided for typical applications in
• Read rate to the NVM blocks
Operating Mode, Standby Mode, and Sleep Mode
P
Operating Mode
P
Standby Mode
P
Sleep Mode
P
Operating Mode
P
Standby Mode
P
TOTAL
STAT
STAT
STAT
DYN
DYN
P
P
N
N
N
N
N
STAT
DYN
NVM-BLOCKS
QUADS
INPUTS
OUTPUTS
PLLS
= P
= P
= P
= P
= P
= P
CLOCK
XTL-OSC
DC1
DC2
DC3
is the total dynamic power consumption.
is the total static power consumption.
is the number of PLLs available in the device.
STAT
is the number of I/O input buffers used in the design.
is the number of Analog Quads used in the design.
+ (N
is the number of I/O output buffers used in the design.
+ P
+ P
NVM-BLOCKS
is the number of NVM blocks available in the device.
DYN
S-CELL
+ P
C-CELL
* P
TOTAL
DC4
+ P
) + P
NET
STAT
+ P
DC5
DYN
INPUTS
+ (N
QUADS
+ P
OUTPUTS
A d v a n c e d v 1 . 4
* P
DC6
+ P
) + (N
MEMORY
INPUTS
+ P
* P
PLL
DC7
+ P
) + (N
NVM
Table 3-13 on page
OUTPUTS
+ P
XTL-OSC
Table 3-14 on page
* P
+ P
DC8
Table 3-14 on page
RC-OSC
) + (N
3-20.
PLLS
+ P
AB
* P
DC9
3-20.
)
3-20.