afs600 Actel Corporation, afs600 Datasheet - Page 71

• Manufacturer Part Number: afs600
• Description: Actel Fusion Programmable System Chips Mixed-signal Family With Optional Arm Support
• Manufacturer: Actel Corporation

RAM512X18 exhibits slightly different behavior from
RAM4K9, as it has dedicated read and write ports.
WW and RW
These signals enable the RAM to be configured in one of
the two allowable aspect ratios
Table 2-30 • Aspect Ratio Settings for WW[1:0]
WD and RD
These are the input and output data signals, and they
are 18 bits wide. When a 512×9 aspect ratio is used for
write, WD[17:9] are unused and must be grounded. If
this aspect ratio is used for read, then RD[17:9] are
undefined.
WADDR and RADDR
These are read and write addresses, and they are nine
bits wide. When the 256×18 aspect ratio is used for write
or read, WADDR[8] or RADDR[8] are unused and must be
grounded.
WCLK and RCLK
These signals are the write and read clocks, respectively.
They are both active high.
WEN and REN
These
respectively. They are both active low by default. These
signals can be configured as active high.
RESET
This active low signal resets the output to zero, disables
reads and/or writes from the SRAM block, and clears the
data hold registers when asserted. It does not reset the
contents of the memory.
PIPE
This signal is used to specify pipelined read on the
output. A LOW on PIPE indicates a nonpipelined read,
and the data appears on the output in the same clock
cycle. A HIGH indicates a pipelined read, and data
appears on the output in the next clock cycle.
Clocking
The dual-port SRAM blocks are only clocked on the rising
edge. SmartGen allows falling-edge-triggered clocks by
adding inverters to the netlist, hence achieving dual-port
SRAM blocks that are clocked on either edge (rising or
falling). For dual-port SRAM, each port can be clocked on
either edge or by separate clocks, by port.
WW[1:0]
01
10
00, 11
signals
are
the
RW[1:0]
00, 11
01
10
write
(Table
and
2-30).
read
Reserved
256×18
512×9
D×W
enables,
A d v an c ed v1 . 4
Fusion devices support inversion (bubble pushing)
throughout the FPGA architecture, including the clock
input to the SRAM modules. Inversions added to the
SRAM clock pin on the design schematic or in the HDL
code will be automatically accounted for during design
compile without incurring additional delay in the clock
path.
The two-port SRAM can be clocked on the rising edge or
falling edge of WCLK and RCLK.
If negative-edge RAM and FIFO clocking is selected for
memory macros, clock edge inversion management
(bubble pushing) is automatically used within the Fusion
development tools, without performance penalty.
Modes of Operation
There are two read modes and one write mode:
RAM Initialization
Each SRAM block can be individually initialized on
power-up by means of the JTAG port using the UJTAG
mechanism (refer to the
page 2-207
note). The shift register for a target block can be selected
and loaded with the proper bit configuration to enable
serial loading. The 4,608 bits of data can be loaded in a
single operation.
• Read Nonpipelined (synchronous—1 clock edge):
• Read Pipelined (synchronous—2 clock edges): The
• Write (synchronous—1 clock edge): On the write
In the standard read mode, new data is driven
onto the RD bus in the same clock cycle following
RA and REN valid. The read address is registered
on the read port clock active edge, and data
appears at RD after the RAM access time. Setting
PIPE to OFF enables this mode.
pipelined mode incurs an additional clock delay
from the address to the data but enables
operation at a much higher frequency. The read
address is registered on the read port active clock
edge, and the read data is registered and appears
at RD after the second read clock edge. Setting
PIPE to ON enables this mode.
clock active edge, the write data is written into
the SRAM at the write address when WEN is HIGH.
The setup times of the write address, write
enables, and write data are minimal with respect
to the write clock. Write and read transfers are
described with timing requirements in the
Characteristics" section on page 2-58
"FIFO Characteristics" section on page
and the
Actel Fusion Programmable System Chips
Fusion SRAM/FIFO Blocks
"JTAG IEEE 1532" section on
2-69.
application
and the
"SRAM
2-57