tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 114

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table 117. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)
114
Address
0x4004A
Bit
8
7
6
5
4
3
2
1
0
TMUX_TTOAC_D13MODE
TMUX_TTOAC_OEPMON
TMUX_TTOAC_D4TO12
TMUX_TTOAC_D1TO3
TMUX_TTOAC_AVAIL
TMUX_TTOAC_S1
TMUX_TTOAC_E2
TMUX_TTOAC_E1
(continued)
TMUX_TTOAC_F1
Name
Transmit TOAC DCC1 to DCC3 Only Mode.
When 1, causes DCC1 to DCC3 in the outgoing
frame to be inserted from the TTOAC channel. The
TTOAC clock rate is 260 kHz. If this control bit is a
logic 0 and TMUX_TTOAC_D13MODE is a logic
zero, then the transmit TOAC channel is in full
access mode.
Transmit TOAC Available Byte Control. When 1,
causes the incoming TOAC values for undefined
bytes (bold-faced bytes in
into the outgoing STS-3/STM-1 frame. Otherwise,
their values depend on SMPR_OH_DEFLT
(Table
Transmit TOAC S1 Byte Control. When 1, causes
the incoming TOAC S1 value to be inserted into the
S1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSS1INS
serted. If the S1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC F1 Byte Control. When 1, causes
the incoming TOAC F1 value to be inserted into the
F1 byte of the outgoing STS-3/STM-1 frame if the
TMUX_THSF1INS
serted. If the F1 is not inserted from register control
or from the transmit TOAC channel, then its value
depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control. When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Other-
wise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC E1 Byte Control. When 1, causes
the incoming TOAC E1 value to be inserted into the
E1 byte of the outgoing STS-3/STM-1 frame. Other-
wise, the E1 value depends on SMPR_OH_DEFLT.
Transmit TOAC D4 to D12 Byte Control. When 1,
causes the TTOAC values to be inserted into the D4
to D12 bytes of the outgoing frame. If this control bit
is a logic zero, then the outgoing D4 to D12 values
depend on SMPR_OH_DEFLT.
Transmit TOAC D1 to D3 Byte Control. When 1,
causes the TTOAC values to be inserted into the D1
to D3 bytes of the outgoing frame. If this control bit is
a logic zero, then the outgoing D1 to D3 values
depend on SMPR_OH_DEFLT.
Transmit TOAC Odd or Even Parity Monitor. When
1, forces the input TOAC parity checker to check for
odd parity; otherwise, even parity is checked on the
transmit TOAC channel.
67).
(Table
(Table
Function
107) control bit is desas-
107) control bit is deas-
Table
523) to be inserted
Agere Systems Inc.
May 2001
Default
Reset
0
0
0
0
0
0
0
0
0