tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 18

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Table 5. Telecom Bus (Low-speed I/O) Pin Description (continued)
18
W2, W1, W3, Y4,
Y2, Y1, Y3, AA4
AA2
AA3
AB2
AB4
AB3
AC2
AC1
Pin
TLSDATAI[7:0]
RLSSYNC52
TLSJ0J1V1
TLSSPE
TLSCLK
TLSPAR
RLSC52
Symbol
(continued)
TLSV1
Type
—
—
—
—
—
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Transmit Low-speed Data (7:0). This is a parallel data
bus. It is used to connect the upstream STS-1 signals from
the slave devices to the master device. In master mode,
TLSDATA is an input bus, eight bits wide. It contains all the
transmit STS-1 data from the slave devices. In slave mode,
these pins are outputs and should be connected to the
TLSDATA(7:0) inputs on the master. TLSDATA contains
three byte-interleaved STS-1 time slots. The slot used by
each SPE mapper in the slaves and the master device, is
determined by programing the SPE_TSTS3_TMSLOT reg-
ister bits.
Transmit Low-speed Clock. This is a 19.44 MHz or
6.48 MHz clock for the TLSDATA(7:0) bits. TLSCLK is an
output on a master Super Mapper and an input on a slave.
Note: As outputs, these pins have 6 mA drive capability.
Transmit Low-speed Parity. This parity bit is generated on
the TLSDATA(7:0) bits output from slave devices and input
to the master Super Mapper. May be configured for odd or
even parity generation or for checking.
Transmit Low-speed SPE Marker. High while the STS-1
payloads are present on the TLSDATA(7:0) bus. Low while
the STS-1 overhead is present on the TLSDATA(7:0) bus.
An output from the master and input on the slaves.
Transmit Low-speed J0/J1/V1 Marker. Transmit J0, J1, or
V1, timing indicator. High while the J0, J1 or V1 bits are
present on the TLSDATA(7:0) bus. An output on the master
and input on slaves.
Transmit Low-speed V1 Marker 3. Transmit V1 timing indi-
cator. High while the V1 bits are present on the
TLSDATA(7:0) bus. An output on the master and input on
slaves.
Receive Low-speed Clock. When in output (master)
mode, it is the receive side of the 51.84 MHz clock output,
synchronous to the receive high-speed input clock (data).
When in input (slave) mode, it receives a 51.84 MHz clock
input, synchronous to the receive high-speed input clock
(data).
Note: As outputs, these pins have 6 mA drive capability.
Receive Low-speed Sync. When in output (master) mode,
it is the receive side frame sync output synchronous to a
51.84 MHz output. When in input mode, it is the receive
side frame sync input synchronous to a 51.84 MHz input.
Description
Agere Systems Inc.
May 2001