tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 548

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
22 Cross Connect (XC) Block Functional Description
The DS3 external device pins may be configured to provide DS3 access to the M13, test-pattern generator, or SPE
mapper.
Table 611. DS3 Interface Programmable I/O
The SONET path overhead access channel (POAC) is configurable for access to the SPE mapper or TMUX.
Table 612. Transmit and Receive POAC Programmable I/O
22.4 Cross Connect Connectivity Overview
Table 613 below describes the connectivity within the cross connect block.
Table 613. Connectivity Within the Cross Connect Block
Notes:
1. Framer, M13, and VT mapper have limited self-loopback capability (no reordering).
2. RAI paths and frame sync paths supported.
3. Framer also has limited test-pattern capability.
4. Auto-AIS paths (fast AIS) supported.PTRADJ paths supported.
5. PTRADJ paths supported
6. Jitter attenuator reordering or cascading (chaining) not expected.
7. Reference clock sources from DJA used by TPG.
8. Prohibited for DS3.
548
Jitter Attenuation
Framer RP_T
Framer TP_T
Destination
External I/O
VT Mapper
Framer TS
M13 MUX
Source
TPG
SPE
DS3POSDATAOUT
DS3NEGDATAOUT
DS3DATAOUTCLK
DS3NEGDATAIN
DS3POSDATAIN
DS3DATAINCLK
RPOACSYNC
TPOACSYNC
RPOACDATA
TPOACDATA
Pin Symbol
Pin Symbol
RPOACCLK
TPOACCLK
NSMI/DS3
External
I/O
%
%
%
%
%
&
T
J
Framer
RP_R
%
T&
%
%
X
X
X
T
J
2, 4
4
Framer
TP_R
T&
%
%
X
X
X
T
X
J
Framer
RS
T&
%
X
X
X
X
X
X
X
Input/Output
Input/Output
Mapper
O
O
O
O
O
O
O
I
I
I
I
I
M13
X
DS3
%
%
%
X
X
1
T
J
&
Mapper
(continued)
X
VT
%
%
%
%
X
1
X
T
J
2
&
Attenuation
Jitter
%
%
X
%
%
%
X
X
T
4, 5
6
4
Agere Systems Inc.
M22
AD4
AD5
AC5
K22
R22
P22
N22
AE3
AF4
AE4
Pin
J22
Pin
SELF
TPM
J T
T
T
T
X
T
T
T
3
7
May 2001
8
NSMI
SPE
DS
X
X
X
X
X
X
X
3