tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 219

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
11 M13/M23 MUX/DeMUX Registers
Table 272. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W)
Table 273. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W)
Table 274. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W)
Agere Systems Inc.
0x1007D
0x1007C
Address
0x1007B
Address
0x1007E
Address
0x1007F
0x10081
0x10083
0x10085
0x10087
0x10080
0x10082
0x10084
0x10086
0x10088
0x10089 15:2
15:8
15:4
7:6
3:0
3:0
Bit
Bit
Bit
5
4
1
0
M13_DEMUXCH2_
M13_DS2_FERR_
M13_DS2_MODE
M13_DS1_OUT_
MODE[1—7][1:0]
M13_M12DMX_
M13_TDS1_
4_INV[1—7]
TYPE[1—7]
EDGE[28:1]
M13_OUT_
AIS[28:1]
MODE
Name
Name
Name
—
—
—
Reserved.
00 = The M12 DeMUX Receives DS2 Signal From the M23
DeMUX.
01 = The M12 deMUX operates as an independent demulti-
plexer.
10/11 = The M12 deMUX is idle and outputs are held low.
The Second and Fourth DS1 Outputs from the M12 Demul-
tiplexers are Inverted if these Bits are 1.
Each DS1/E1 Output Selector Number, x, can be
Expressed as Either 4y – 3, 4y – 2, 4y – 1, or 4y, where y
Ranges From 1 to 7. For a given y, the 4 selectors in the
group output DS1 signals if M13_OUT_TYPEy = 1, or E1 sig-
nals if M13_OUT_TYPEy = 0.
The Transmit DS1/E1 Signals are Retimed by the Rising
Edge of the Associated Clocks if these Bits are Set High;
Otherwise, the Data is Retimed By the Falling Edge.
Reserved.
A logic 1 of these bits will cause the corresponding DS1 output
all ones AIS.
Reserved.
This Bit Controls the DS2 Framing Algorithm In the DS1
Mode Only. Out of frame is declared if the F bits contain two
errors in 4 bits if M13_DS2_MODE = 0, or at least 1 F-bit error
in four consecutive M-subframe pairs if M13_DS2_MODE = 1.
This Bit Controls Frame Error Counting for the M12
Demultiplexers in the E1 Mode Only. If this bit is 0, the frame
error counters increment for each frame alignment signal bit
error. Otherwise, the counter increments once for each frame
alignment signal that contains at least 1 bit error.
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
Function
Function
TMXF28155/51 Super Mapper
Default
Default
Default
0x0000
Reset
Reset
0x000
Reset
0x00
0xF
0x0
00
1
1
0
0
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