tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 572

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
23 Digital Jitter Attenuation Controller Functional Description
23.3 Functional Block Diagram of the DJA Block
The functional view of the DJA block, along with interconnections to the other blocks within the Super Mapper
device, are shown in the
The DJA block interfaces only to the cross connect and microprocessor interface blocks within the Super Mapper
device. The input interface between the DJA block and the cross connect block consists of clock, serial data, VT
pointer adjustment indication, and AIS insert indication. The output interface consists of clock, serial data, and AIS
insert indication as well as the DS1 and E1 AIS clocks for use by other blocks within the device.
23.4 Digital Jitter Attenuation Controller Operation
The digital jitter attenuation (DJA) controller is comprised of 28 DJA blocks. The DJA_SEL line rate control register
(Table
The DJA controller requires a reference clock running at 16 or 32 times the line rate of the signal requiring jitter
attenuation. This reference clock should be driven on one of the external input signals DS1XCLK or E1XCLK (see
Table 3, High-speed I/O Pin Descriptions on page15
Each jitter attenuator block receives a clock, data, pointer adjust control, and an AIS control signal input. If the AIS
control signal is active (high) on any time slot, then the AIS clock generation block (see
ply divides the correct line clock (XC_JCLKx) by 16 or 32 (via the DJA_BLUECLKD register shown in
independent of being in DS1 or E1 mode), sends this divided clock (DS1_AISCLK or E1_AISCLK) to the cross con-
nect, and transmits the data signal (DJA_DATA) as a continuous logic 1.
Even with the digital PLL portion of the DJA turned off (via the P_DJA_CLK_EN register, see
the AIS clock generation block will still generate the correct DS1_AISCLK or E1_AISCLK signals.
Each DJA block has a 64-bit elastic store. These elastic stores are monitored for both underflow and overflow con-
ditions. Both of these conditions contribute to the DJA_ESOVFL parameter, which can be unmasked to contribute
to an interrupt DJA_ESOVFL[28:1]
center itself.
The block monitors DS1XCLK (DJA_DS1LOC and DJA_G_DS1LOC) and E1XCLK (DJA_E1LOC and
DJA_G_E1LOC) for loss of clock (LOC indication,
Table
clock generation block, while the DJA_G_DS1LOC and DJA_G_E1LOC parameters are controlled by LOC events
detected at the DPLL. All loss of clock indications can contribute to a DJA interrupt. These interrupts can be
unmasked by writing zeros to the registers in
Underflow Masks (R/W) on page
572
469). The DJA_DS1LOC and DJA_E1LOC parameters are controlled by LOC events detected at the AIS
478) is used to determine if the block is operating in the DS1 or E1 mode (1 = DS1, 0 = E1).
XC_JAISx
XC_JCLKx
XC_JDATAx
XC_JPTRADJx
DS1_XCLK
E1_XCLK
Figure
Figure 99. Basic Functional Flow of the DJA Block
99.
332.
(Table
469). In the event of an elastic store overflow, the elastic store will re-
Table 470, DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/
BLOCK REPEATED 28 TIMES
Table
under the M13 MUX/DEMUX block receive path section).
ATTENUATION
471) and change of loss of clock state (LOC delta,
JITTER
BLOCK
GENERATION
AIS CLOCK
DJA_CLKx
DJA_DATAx
DJA_AUTOAISx
DS1_AISCLK
E1_AISCLK
Figure
(continued)
Table 71 on page71
99) of the DJA sim-
Agere Systems Inc.
Table
May 2001
5-8956(F)r.1
479,
,