tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 594

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
26 Applications
(continued)
Within the M23 demultiplexer, there are four performance monitoring counters for F- or M-bit, P-bit, E-bit parity, and
FEBE errors. Each M12 demultiplexer contains two performance monitoring counters.
26.9.2 Transmit Direction
The incoming DS1/E1 clocks are first checked for activity or loss of clock (LOC). The data signals are retimed and
checked for AIS and activity. DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs
from the deMUX path to be looped back. This loopback can be performed automatically or the user can force a
DS1 or E1 loopback.
The four DS1 or three E1 signals for each M12 MUX are fed into single bit 16-word-deep FIFOs to synchronize the
signals to the DS2 frame generation clock. The fill level of each FIFO determines the need for bit stuffing its
DS1/E1 input. The M13 can handle DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to five unit
intervals peak jitter. The DS2/DS3 transmit clock is used to derive the clock source for DS2 frame generation.
The M23 multiplexer generates a transmit DS3 frame, and fills the information bits in the frame with data from the
seven DS2 select blocks. The M23 MUX can be provisioned to operate in either the M23 mode or the C-bit parity
mode. It contains seven DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need for bit
stuffing its DS2 input.
The transmit DS3 output can either be in the form of unipolar clock and data or unipolar clock, positive and negative
data. The DS3 data is B3ZS encoded and can be looped back from the receive DS3 input.
26.10 Cross Connect Block
The cross connect (XC) is a highly configurable nonblocking crosspoint switch for DS1/E1/DS2 signals, configura-
tion of DS3 signal paths, and configuration of the path overhead access I/O. The cross connect plays a major role
in configuring the interconnection of major function blocks to satisfy an application’s implementation.
The cross connect provides the flexibly to tie DS1/E1/DS2 channels from the framer or external pins to the M13
mapper or to the VT mapper. It is also capable of multicast or broadcast operation (one port to many), handling
injected test patterns, idles, or alarm conditions to any channel, and can provide system loopback testing support.
Jitter attenuation may also be inserted in-line on any DS1/E1 channel.
The cross connect can interconnect up to 28 individual DS1/E1 channels between the framer, M13 multiplexer, VT
mapper, jitter attenuator, or external I/O. The external I/O pins support an application dependent mix of up to
29 T1/E1 interfaces (one dedicated protection channel), seven DS2 interfaces, or one of four available framer sys-
tem interfaces.
The cross connect supports an independent signal path for remote alarm indication (RAI), alarm indication signal
(AIS), and byte-synchronous frame sync signals on channels between the VT mapper or M13 and the framer.
Receive pointer adjustment information is routed to the jitter attenuator block for each channel originating in the VT
mapper.
The cross connect has independent DS2 interfaces for the M12 and M23 blocks of the M13 MUX. Full split access
to the external I/O device pins provides the capability to add, drop, or rearrange the DS2 signals within the M13.
For DS3 signals, the cross connect supports configuration of interconnects between the M13 and the SPE, or
external I/O interconnection to the M13 or SPE, or insertion/monitoring of DS3 test patterns from the test-pattern
generator block.
The test-pattern generator block (TPG) provides test signals and it monitors inputs (TPM) for signals to and from
the cross connect. The TPG can generate a set of test signals or idles at DS1, E1, DS2, or DS3 rates. There is only
one test pattern generator and monitor per signal rate.
Device pins for the path overhead access channel may be configured to connect to the SPE mapper or TMUX
blocks.
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Agere Systems Inc.