tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 502

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.16 Transmit Signaling Global Feature Provisioning
The transmit signaling processor requires the provisioning of one global item in order to enable signaling extraction
and delivery.
21.16.1 Link-Count Selection
The link count is specified by programming FRM_T_LINKCNT[4:0] in FRM_SGR8, transmit signaling global regis-
ter 8 (R/W),
cation. A value of 21 is appropriate for a 21 link CEPT application. If the application mixes DS1 and CEPT links or
the TDM clock supplied to the framer is less than 51.84 MHz, this value should match the terminal count
(FRM_TC[7:0]) set in FRM_FGR2, framer global register 2 (R/W),
21.17 Other Transmit Signaling Global Features
21.17.1 Support of Automatic Signaling Freeze on Framing Bit Errors
This feature is valid when extracting signaling from the receive line interface (transport mode). By default, signaling
extraction from a particular receive line will halt when the appropriate alignment has been lost. In order to guaran-
tee that signaling freeze takes place as soon as possible, FRM_T_AFZFBE in FRM_SGR8, Transmit Signaling
Global Register 8 (R/W), bit 1, must be set to 1. When enabled, FRM_T_AFZFBE halts signaling extraction for 32
frames upon detection of a frame bit error. When FRM_T_AFZFBE is enabled, the transmit signaling debounce
feature must also be enabled. The FRM_T_SIGDEB feature is enabled in FRM_TSLR32, Transmit Signaling Link
Register 32 (R/W), bit 5.
21.17.2 Support of Byte Sync SONET Mapping
A provisionable feature related to SONET byte sync mapping requires that those time slots which are configured
for no-signaling should have a signaling value of 0 transported by the VT mapper. This feature can be enabled by
setting FRM_T_SUBZERO in FRM_SGR8, Transmit Signaling Global Register 8 (R/W), bit 5, to 1. In that case,
those time slots with a signaling state mode of no-signaling (GF = 10) will automatically forward a value of 0 to the
VT mapper.
21.18 Transmit Signaling Status Registers
There are two status values which are maintained for each of the links.
21.18.1 Maintenance of CEPT Related Status Bits
There are 2 bits which reflect the status of the CEPT time slot 16 signaling multiframe. These status bits are valid
when the source of signaling is set to be the receive line interface (transport mode). The location of these status
bits is in FRM_TSLR33, Transmit Signaling Link Register 33 (COR),
502
Link Count (number of active transmit links).
The receive signaling register searches for AIS in time slot 16 when time slot 16 alignment is lost. The status of
this search is maintained.
The status of TS16 multiframe alignment is maintained.
Table 366 on page265
, bits [14:10]. The reset value is 28, which is appropriate for a 28 link DS1 appli-
Table 306 on page246
Table 379 on page273
(continued)
, bits [7:0].
.
Agere Systems Inc.
May 2001