tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 406

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
18 SPE Mapper Functional Description
(continued)
LINE_TXCLK29
TXDATAEN
VARIABLE
TXSYNC (OPTIONAL)
UNUSED
LINE_TXDATA29
0785(F)(F)
Figure 34. STS-1 NSMI Transmit Operation
18.12 TMUX Interface to the SPE Mapper
The SPE mapper sends/receives data mapped as an AU-3/STS-1 SPE signal or as a TUG-3 signal to/from the
TMUX. The interface required for this exchange of data, clock, and control signals is called the high-speed telecom
bus. The high-speed telecom bus is accessible from external pins so that the TMUX can send/receive data to/from
other external Super Mapper devices in the system. The TMUX can byte interleavingly multiplex three STS-1s or
three TUG-3 signals, receiving through the telecom bus, to form one STS-3 or STM-1 signal, respectively.
The high-speed telecom bus consists of a byte-wide data bus running at 19.44 Mbits/s for STS-3/STM-1 mode, or
6.48 Mbits/s for STS-1 stand-alone mode. It also consists of a parity bit line, a clock line which is 19.44 MHz or
6.48 MHz depending on STS-3/STM-1 or STS-1 mode, respectively; one sync line and two sync control lines. The
sync line outputs the J0, J1, and V1 time slot signals of the STS-3/STM-1 frame and the two sync control signals
distinguishes between the three sync bytes. The sync signals are used to synchronize the byte counters in the SPE
mapper, and the information is also passed along to the VT mapper for synchronizing the V1 counters.
The TMUX also provides through the external pins one 51.84 MHz serial clock and one clock control signal which
synchronizes the 51.84 MHz to the J0 byte of the STS-3/STM-1 frame. This serial clock is required for the M13
MUX/deMUX because of its serial mode of working.
In the case where the SPE mapper has to drive the telecom bus in the transmit side, there is a 3-state control sig-
nal (active-high) which is an output from the SPE mapper. This signal enables the 3-state drivers on the high-speed
telecom bus at the time period when the clock is low.
18.13 PATH Termination Block
The path termination block of the SPE mapper is shown below. The block consists of a pointer interpreter which
monitors the TU-3 pointer bytes H1, H2, and H3, and interprets the beginning of the path overhead bytes for the
TUG-3 frames. After monitoring and terminating the path overhead bytes, the TUG-3 payload is passed on to the
output blocks.
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Agere Systems Inc.