tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 275

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
12 28-Channel Framer Registers
Table 384. FRM_PMLR3, Performance Monitor Link Register 3 (R/W)
* See
Table 385. FRM_PMLR4, Performance Monitor Link Register 4 (COR)
Agere Systems Inc.
Address*
Address*
0x8LP83
0x8LP82
Table 381
15:11
for values of L and P.
10:7
Bit
15
14
13
4:0
Bit
6
5
FRM_MHGALIGN[3:0] Handling Group Alignment Interrupt Mask. A 1 masks
FRM_PM_IM6[15:0]
FRM_SLIPO
FRM_SLIPU
FRM_OOF
FRM_MSEFS
Name
FRM_MFE
Name
—
Receive Elastic Store Slip Overflow. A 1 indicates that the
receive elastic store performed a control slip due to an elastic
store overflow condition. This signal is set when the error occurs
and is cleared when it is read, if there is not another error during
the read.
Receive Elastic Store Slip Underflow. A 1 indicates that the
receive elastic store performed a control slip due to an elastic
store underflow condition. This signal is set when the error
occurs and is cleared when it is read, if there is not another
error during the read.
Out Of Frame. A 1 indicates that the receive framer has lost
frame alignment and is currently searching for a new frame
alignment.
page 488
(T1.231 section 6.1.2.2.1, G.706 section 4.1). Excessive
(exceeding the provisionable CRC error count) CRC errors may
optionally cause a reframe.
In ESF or J-ESF, more than 320 CRC-6 errors in 1 second
result in loss of frame alignment. The CRC error count is provi-
sionable.
In the CEPT CRC-4 multiframe formats, more than 915 CRC-4
errors in 1 second result in loss of frame alignment. (G.706 sec-
tion 4.3.2). The CRC error count is provisionable.
Reserved. Must write to 0.
the corresponding status bit in the interrupt status register
(Table
interrupt to be generated.
Severely Errored Frame Interrupt Mask. A 1 masks the
corresponding status bit in the interrupt status register
(Table
interrupt to be generated.
CEPT Functional Element Status Interrupt Mask. A 1
masks any and all of the FE status bits in
Table 395
interrupt to be generated.
Performance Monitor Register FRM_PMLR6 Interrupt
Mask. A 1 masks the corresponding status bit in the inter-
rupt status register
rupt. A 0 allows an interrupt to be generated.
(continued)
lists the loss of frame criteria for the framing bit.
Section 21.6.1 Loss of Frame Alignment Criteria on
400) from generating an interrupt. A 0 allows an
400) from generating an interrupt. A 0 allows an
from generating an interrupt. A 0 allows an
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table
Function
Function
387) from generating an inter-
TMXF28155/51 Super Mapper
Table 394
and
Default
Default
0x001F
Reset
Reset
00000
0xF
0
0
0
1
1
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