tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 128

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
8 TMUX Registers
Table 143. TMUX Register Map (continued)
Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.
128
Addr. Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
0x4004A
0x4004B
0x4004D
0x4004E
0x4004F
0x40048
0x40049
0x40050
0x40051
0x40052
0x40053
0x40054
0x40055
0x40056
0x40057
0x40058
0x40059
TMUX_TBERI
TMUX_TOAC
TMUX_RPOA
TMUX_THS_
TMUX_TFRA
TMUX_SD_C
TMUX_SD_C
TMUX_SD_C
TMUX_SD_C
TMUX_SD_C
TMUX_SD_C
TMUX_SF_C
TMUX_SF_C
TMUX_SF_C
TMUX_SF_C
TMUX_SF_C
TMUX_SF_C
MEOFFSET
ERR_CTL
NS_CTL
C_CTL
_CTL
TL1
TL2
TL3
TL4
TL5
TL6
TL1
TL2
TL3
TL4
TL5
TL6
OAC_D412
TMUX_RT
MODE
TMUX_RPOAC_
SEL[1:0]
TMUX_TLBITCNT[2:0]
(continued)
TMUX_RT
OAC_D13
MODE
RTOAC_
RPOAC_
OEPINS
OEPINS
TMUX_
TMUX_
TMUX_TPS
TMUX_TLSTSCNT[1:0]
LREIINS
TMUX_TPS
TMUX_SDMCLEAR[7:0]
TMUX_SFMCLEAR[7:0]
B2EINS
TMUX_SDMSET[7:0]
TMUX_SFMSET[7:0]
Transmit High-speed Error Insertion Control Parameters—R/W
Receive/Transmit TOAC/POAC Control Parameters—R/W
B1/B2 Signal Degrade Set/Clear Control Registers—R/W
Transmit High-speed Offset Control Parameters —R/W
B1/B2 Signal Fail Set/Clear Control Registers—R/W
TMUX_TPREIINS[3:1]
D412MODE
TMUX_TAP
TMUX_TPOAC_SEL[1:0]
SBABINS
TTOAC_
Bit 9
TMUX_
TMUX_SDNSCLEAR[18:3]
TMUX_SFNSCLEAR[18:3]
D13MODE
TMUX_SDBCLEAR[15:0]
TMUX_SFBCLEAR[15:0]
TMUX_SDNSSET[18:3]
TMUX_SFNSSET[18:3]
TTOAC_
Bit 8
TMUX_
TMUX_SDBSET[15:0]
TMUX_SFBSET[15:0]
TMUX_TH1H2INVEN[3:1]
TMUX_TLCOLCNT[6:0]
TMUX_TTO
AC_AVAIL
Bit 7
TMUX_THSB3ERRINS[3:1]
TMUX_TTO
TMUX_TP
OAC_N1
Bit 6
AC_S1
TMUX_TH1
TMUX_TTO
H2INVORN
TMUX_TP
TMUX_SDLCLEAR[3:0]
TMUX_SFLCLEAR[3:0]
OAC_K3
Bit 5
AC_F1
TMUX_SDLSET[3:0]
TMUX_SFLSET[3:0]
DF
TMUX_TLR
TMUX_TTO
TMUX_TP
Bit 4
OAC_F3
AC_E2
EIINS
TMUX_TTO
TMUX_TP
OAC_F2
Bit 3
AC_E1
Preliminary Data Sheet
TMUX_THSB2ERRINS[3:1]
TMUX_TA2ERRINS[4:0]
TMUX_TP
TMUX_TLROWCNT[3:0]
TTOAC_
D4TO12
OAC_C2
Bit 2
TMUX_
TMUX_SDNSCLEAR[2:0]
TMUX_SFNSCLEAR[2:0]
Agere Systems Inc.
TMUX_SDNSSET[2:0]
TMUX_SFNSSET[2:0]
TMUX_TTO
AC_D1TO3
TMUX_TP
OAC_J1
Bit 1
May 2001
TMUX_THS
B1ERRINS
OEPMON
OEPMON
TPOAC_
TTOAC_
Bit 0
TMUX_
TMUX_