tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 394

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

TMXF28155/51 Super Mapper
Preliminary Data Sheet
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
May 2001
17 TMUX Functional Description
(continued)
An APS babbling test is controlled with TMUX_TAPSBABINS
(Table 116 on page113
). Setting
TMUX_TAPSBABINS = 1 forces the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are con-
tinuously the same.
When the transmit K2 software insert bit TMUX_THSK2INS = 1
(Table 107 on page103
), data from bits
TMUX_TK2INS[2:0]
(Table 113 on page110
) is written into the K2[2:0] output bits. When TMUX_THSK2INS = 0,
hardware insertion of RDI-L is enabled.
17.6.20 Criteria for Insert Line RDI
Hardware insertion of line RDI is generated using the following equation. Each defect contribution to line RDI can
be individually inhibited.
(TMUX_RILOC AND TMUX_TRILOC_LRDIINH) OR
(TMUX_RHSLOS AND TMUX_TRLOS_LRDIINH) OR
(TMUX_RHSLOF AND TMUX_TRLOF_LRDIINH) OR
(TMUX_RHSOOF AND TMUX_TROOF_LRDIINH) OR
(TMUX_RLAISMON AND TMUX_TRLAISMON_LRDIINH) OR
(TMUX_RHSSF AND TMUX_TRSF_LRDIINH) OR
(TMUX_RHSSD AND TMUX_TRSD_LRDIINH)
When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L must last for at least
20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
The TMUX provides a protection switch MUX for RDI-L insertion. The MUX is controlled by TMUX_TLREIRDISEL
(Table
107). If TMUX_TLREIRDISEL = 1, then the RDI-L value for insertion is taken from the value on the protec-
tion board rather than from the receive side of the same TMUX.
17.6.21 Line AIS Generation
Line AIS is specified as all ones in the entire STS/STM signal before scrambling, excluding the section overhead.
Line AIS can be generated by setting TMUX_THSLAISINS = 1
(Table
107).
17.6.22 B2 BIP-8 Calculation and Insert
The B2 byte is allocated for a line overhead error monitoring function. This function will be a bit interleaved parity-8
code (BIP-8) using even parity. The BIP-8 is computed before scrambling, over all the bits of the previous STS-1
frame (except for the 9 bytes of section overhead) and is placed in byte B2 of the current frame also before scram-
bling.
A bit error rate can be inserted on any B2 byte. When bit(s) TMUX_THSB2ERRINS[1—3]
(Table 115 on page112
)
is (are) asserted, the corresponding B2 byte is inverted each time the microprocessor interface block
SMPR_BER_INSRT
(Table 65 on page66
) bit is asserted.
17.6.23 F1 Byte Insert
When TMUX_THSF1INS = 1
(Table 107 on page
103), the value in TMUX_TF1INS[7:0]
(Table 112 on page
110) is
inserted into the F1 byte of the outgoing signal. Otherwise, the associated TOAC value is inserted when
TMUX_TTOAC_F1 = 1
(Table 117 on page113
). If both TMUX_THSF1INS and TMUX_TTOAC_F1 = 0, then the
value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT
(Table 67 on page
68)
bit. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
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Agere Systems Inc.