tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 576

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
24 Test-Pattern Generation/Detection Functional Description
24.4 Block Diagram
The following diagram illustrates the high-level interface between the TPG block and other functional blocks.
24.5 Functional Descriptions
24.5.1 Test-Pattern Generation
The test-pattern generator has five groups of output signals. These outputs consist of two signal groups for DS1
and one signal group each for E1, DS2, and DS3 clock rates. Each of these groups can be provisioned, indepen-
dently, in various ways. Each DS1/E1 signal group consists of a clock, the data stream, and a frame-sync signal (if
needed in a byte-synchronous environment). The DS2 signal group consists of clock and data. The DS3 signal
group consists of data, clock, and clock enable. Each rate supports full-payload test patterns data signals and DS1
also supports continuous idle data signals.
576
CONTROL INTERFACE
GEN/MON
TEST
TPG
Figure 100. TPG Block Interface Block Diagram
3
3
3
3
3
DS1/E1/DS2/DS3 SOURCE CLOCKS
(TPG_DS3) DATA/CLK/CLKEN
(TPG_DS1) DATA/CLK/SYNC
(TPG_DS1) IDLE/CLK/SYNC
(TPG_E1) DATA/CLK/SYNC
[DS3} DATA/CLK/CLKEN
(DS1) DATA/CLK/SYNC
(DS1) IDLE/CLK/SYNC
(TPG_DS2) DATA/CLK
(E1) DATA/CLK/SYNC
(DS2) DATA/CLK
2
3
4
3
3
3
CONNECT
CROSS
(continued)
XC
Agere Systems Inc.
May 2001
5-9178(F)r.3