tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 435

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description
Pointer increments and decrements are monitored and counted internally. The performance monitoring reset signal
transfers the count to the holding registers for pointer increment (VT_PTR_INC[1—28][3:0]
pointer decrement (VT_PTR_DEC[1—28][3:0]
registers to 0. When SMPR_SAT_ROLLOVER = 1
mum value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if
the SPE mapper is requesting AUTO AIS or VT_LOP[1—28] = 1 (loss of pointer)
(VT AIS)
LOP-V (VT_LOP) and AIS-V (VT_AIS) will be detected and reported to the microprocessor. Both the LOP-V and
AIS-V conditions will contribute to the VT/TU mapper automatic AIS generation that is driven over a 28-bit internal
output bus to the cross connect (XC). Any change in state of VT_LOP or VT_AIS will be reported to the micropro-
cessor via VT_LOP_D[1—28] and VT_AIS_D[1—28]
(VT_LOP_M[1—28] or VT_AIS_M[1—28])
ate an interrupt.
A check for VT/TU size mismatches is performed by comparing the expected VT/TU size bits (VT1.5 = 11,
VT2 = 10) with the actual received SS bits in the V1 byte. After three consecutive mismatches, size errors will be
reported with bit VT_SIZERR[1—28]
bit VT_SIZERR_D[1—28]
VT_SIZERR_D[1—28] = 1 will generate an interrupt.
The accepted pointer is stored and accessible by the microprocessor.
This block supports tributary loopback.
19.9 VT Termination (VTTERM)
The VTTERM logic block (in
The following features are implemented.
19.9.1 V5 Termination
The V5 byte is checked for BIP-2 errors. If BIP-2 errors are detected, REI-V is transmitted in the V5 byte of the cor-
responding transmit VT, if enabled by bit VT_REI_EN[1—28] = 1
in the V5 byte is counted on a per-superframe basis. BIP-2 errors can counted on either a bit or block basis
selected by bit, VT_BIT_BLOCK_CNT (1 = bit, 0 = block)
Agere Systems Inc.
The pointer interpreter will transition into the DEC state based on the following conditions:
— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1
— If NDF is enabled on the incoming V1 and V2 bytes, the pointer interpreter will transition from the DEC state
— Following three consecutive superframes with all ones in the V1 and V2 bytes, the pointer interpreter will tran-
— Following three new consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the
— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0]
The pointer interpreter will transition out of the DEC state based on the following conditions:
for a pointer decrement on the incoming V1 and V2 bytes, the pointer interpreter will transition into the DEC
state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming V1
and V2 bytes, the pointer interpreter will transition into the DEC state.
into the NDF state.
sition from the DEC state into the AIS-V state.
DEC state into the NORM state.
DEC state into the NORM state.
pointer interpreter will transition from the DEC state into the LOP-V state.
(Table
177) (or VT_H4LOMF = 1 (loss of H4 multiframe alignment)
(Table
Figure
169). Unless the VT_SIZERR_M[1—28]
39) will perform all necessary functions to support complete VT/TU termination.
(Table
(Table
177). Any change in state of VT_SIZERR[1—28] will be reported with
(Table
173), VT_LOP_D[1—28] = 1 or VT_AIS_D[1—28] = 1 will gener-
(Table
(Table
208)) for microprocessor read and resets the running count
(continued)
67), the internal running counts will hold at their maxi-
(Table
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
169). Unless the appropriate mask bit is set
181).
(Table
(Table
198). BIP-2 errors and reception of REI-V
181)), if 8 of the 10 I and D bits are correct
(Table
(Table
TMXF28155/51 Super Mapper
(Table
173) mask bit is set,
176)).
177) or VT_AIS[1—28] = 1
(Table
(Table
208)), and
183), the
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